The latest developments in networking and the rapidly increasing demand for IoT devices lead to higher demands on time-to-market and production costs. In addition, the complexity of the development processes for smart sensor ASICs is constantly increasing and new methods for automation and code generation are particularly needed in development. This paper describes a new methodology that formalizes functional specification based on SysML and enables automation of Virtual Prototype (VP) development. The virtual prototype is an established approach for early embedded software development. The presented methodology translates natural language written specifications into a modeled and formalized functional specification and enables the generation of behavior descriptions in SystemC that are used for the creation of VP. Furthermore, it enables the connection of the IP-XACT-centric generation of the register interface description, as well as the description of the signal processing parts by MATLAB®Simulink®, with the SysML-based generated functional description.

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults.

In this paper, we present a flow for integrating hardware descriptions into Simulink simulations. It enables the automatic generation of a Simulink component out of a hardware component model given as RT level VHDL. The approach is based on two steps. The first step transforms the VHDL model to SystemC. In contrast to existing VHDL-to-SystemC transformation tools, the readability and configurability of the input model is preserved. In addition, our approach yields a more exact model, as a custom designed VHDL-like data-type system is employed. The second step generates a specific wrapper to allow the use of the component in a Simulink simulation. This transformation strategy will be evaluated with two industrial automotive electronics hardware designs.

In common design flows of mixed-signal ASICs, the transition from system-level models to implementation-level models is executed in a manual process that carries potential for an efficiency gain by automation. This contribution addresses this aspect by showing and discussing an approach for efficient automated transitions from digital parts of Simulink models representing heterogeneous systems to VHDL and Verilog descriptions. It describes a design flow, in which a Simulink model representing a digital part of a mixed-signal ASIC is checked and optimized for automated generation of design rule compliant and more efficient digital hardware implementations. For this purpose, modeling guidelines and optimizations were implemented and integrated into an easily usable graphical user interface. Thereby, the strategy is based on considering and optimizing the digital part with respect to the surrounding heterogeneous system. An evaluation of the presented design flow is shown by applying the flow to an automotive hardware design.

This contribution shows and discusses the requirements and constraints that an industrial engineering process defines for the integration of hardware IP into the system development flow. It describes the developed strategy for automating the step of making hardware descriptions available in a MATLAB/Simulink based system modeling and validation environment. It also explains the transformation technique on which that strategy is based. An application of the strategy is shown in terms of an industrial automotive electronic hardware IP block.

Functional verification is a major part of todaypsilas system design task. Several approaches are available for verification on a high abstraction level, where designs are often modeled using MATLAB/Simulink, as well as for RT-level verification. Different approaches are a barrier to a unified verification flow. For simulation based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This paper describes how this SystemC-based concept can be applied to Simulink models. The implementation of the resulting verification flow addresses the required synchronization of both simulation environments, as well as data type conversion. An example is used to evaluate the implementation and the whole verification flow. It is shown that using the extended verification flow saves a significant amount of time during development. Reusing test bench modules and test cases preserves consistency of the test bench. Verification is done automatically rather than by inspecting the waveform manually. The extended verification flow unifies system-level and RT-level verification, yielding a holistic verification flow.