Device design using Machine Learning has been used in the semiconductor industry over the past ten years. However, the generation of the training data set for precise predictions using this technique remains burdensome. Addressing this, in this work, we propose eight sample-efficient techniques to train the Deep Neural Network (DNN) based surrogate models that emulate Technology Computer-Aided Design (TCAD). We showcase their efficacy by predicting off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) of a Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET). Our findings highlight the potential for 38% reduction in training dataset size while maintaining a strong predictive baseline accuracy. Specifically, the Diverse Representative-Query-by-Committee (DR-QBC) technique works best yielding 6.5% Euclidean Norm of Prediction Error (ENPE). We also demonstrate an inverse design framework by leveraging the same surrogate model with Differential Evolution (DE) and Bayesian Optimizer (BO). It mimics the role of a device design engineer by optimizing the values of structural parameters of the LDMOS transistors such that the desired BVDS,off is attained while minimizing Rsp.

This paper proposes a dead-time control circuit to generate independent and adaptive delays for the rise and fall time duration. The circuit comprises a rise/fall time detector, rise/fall time to voltage converter and switch capacitor-based charge integrator block to generate the adaptive dead-time. The proposed adaptive dead-time controller design implemented using a 0.18μm HV CMOS process, occupies 170μm x 90μm silicon area. The results show good accuracy in the dead-time generation with an error <±3.5ns. In post-layout simulation, the design provides sinusoidal output with a very low offset voltage of 70mV.

The linearity of data converters fabricated in modern CMOS processes is typically limited by device mismatch. The dispersion in device placement primarily determines the extent of matching and hence, the chip yield. Till date, there exists no straightforward approach to precisely quantify dispersion over an array of identically laid out devices. The current research formulates new measures to quantify dispersion in device placement. The incorporation of such measures in traditional CAD optimization results in similar or even better correlation coefficients, but with a lighter computational footprint. This facilitates for faster optimization of large device placements without the need for high end processors.

High speed data converter architectures such as pipelined analog-to-digital-converters (ADCs) typically consist of large capacitor arrays that are highly susceptible to systematic errors. Although significant efforts have been made in the literature to compensate linear and parabolic errors, the rotated parabolic components are less explored. These rotated parabolic components are responsible for spurious harmonics at the output of the converter, thereby degrading the linearity. In this article, we have investigated the origin of these rotated components, their impact on conversion linearity and discussed strategies to mitigate them. A placement technique along with one track routing solution, is proposed for complete compensation of the systematic errors. An algorithm is also provided to extend this technique to higher resolutions. The proposed technique is verified on the model of pipelined ADC, as well as current steering DAC. The incorporation of such technique results in near ideal linearity performance.