Demo Data from VLDB 2026 / reviewers in the wild / expert
Chwan-Chia Wu
dblp:78/733
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Distributed systems · 30% Electronic design automation · 30% Hardware reliability and fault tolerance · 30% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware test
fault localization |
0.0 | 1 | 1987 | Time Redundant Fault-Location in Bit-Sliced ALU's · IEEE Trans. Computers 1987 |
Distributed systems
fault tolerance |
0.0 | 1 | 1987 | Time Redundant Fault-Location in Bit-Sliced ALU's · IEEE Trans. Computers 1987 |
Hardware reliability and fault tolerance › redundancy
time redundancy |
0.0 | 1 | 1987 | Time Redundant Fault-Location in Bit-Sliced ALU's · IEEE Trans. Computers 1987 |
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit |
0.0 | 1 | 1987 | Time Redundant Fault-Location in Bit-Sliced ALU's · IEEE Trans. Computers 1987 |
Methods — techniques the papers use, named apart from their topics
time redundancy · 0.0recomputing with shifted operands · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Performance evaluation for multiple DSSS systems with channel bands overlappedabstractThis paper conducts performance evaluation for a code division multiple access (CDMA) system which is interfered by another neighboring CDMA system. Both systems are assumed to adopt direct-sequence spread-spectrum (DSSS) techniques and have the same carrier frequency. Automatic power control (APC) is assumed to be implemented in the interfered system such that all the users deliver the same power to the receivers. Approximation of the signal to noise ratio (SNR) is derived by which the performance figure can be achieved with least expensive computational cost. By conducting a variety of analyses we show that our analytical formulation is very close to simulation results under certain conditions. Ming-Heui Chen, Bih-Hwang Lee, Chwan-Chia Wu |
PIMRC | 3 |
| 1987 | Time Redundant Fault-Location in Bit-Sliced ALU'sabstractA method of fault location in arithmetic and logic units (ALU's) is proposed. When the failures are confined to adjacent bit slices of the ALU's, the RESO (recomputing with shifted operands) based method can isolate the faulty bit slices by specifying a larger set of ``suspicious'' faulty bit slices, and, therefore, identify the definitely fault-free bit slices in ALU's. The method is applicable to both arithmetic and logic operations. Chwan-Chia Wu |
IEEE Trans. Computers | 1 |