In this paper, we describe special techniques and challenges of implementing large scale logic design models in massively parallel fine-grained multiprocessor systems. We will examine performance of such systems and the methods for improving it by reducing the redundant evaluations, memory mapping optimizations, partitioning and scheduling.

As the density of VLSI circuits increases, software techniques cannot effectively simulate designs through the millions of simulation cycles needed for verification. Emulation can supply the necessary capacity and performance, but emulation is limited to designs that are structural or can be synthesized. This paper discusses a new system architecture that dramatically accelerates event-driven behavioral simulation and describes how it is merged with emulation. 1.1 Keywords reconfigurable computing, event-driven simulation 2.

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Two novel algorithms are presented for calculation of input weights used during weighted random testing. One of them is based on circuit structure analysis, the other one uses pre-generated test patterns to compute weights. These methods provide random tests with high fault coverage and a small number of test vectors. They can be used both for BIST and for external testing of VLSI.>