To meet challenges of deep-subwavelength technologies (particularly 130 nm and following), lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETs like altPSM. For emerging technologies (65 nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the design-silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. We have been exploring how design might take advantage of these restrictions, and present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPC/RET algorithms and the accuracy of models of manufactured products. We also believe that the underlying technology, including simulation and analysis, may be applicable to a variety of approaches to design for manufacturability (DFM).

Integrated logic synthesis and physical design (physical synthesis) continues to play a very important role in high performance microprocessor design methodologies. In this paper, we present the integrated physical synthesis timing closure methodology used in the current generation microprocessors. Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area. The design turn around times were significantly reduced and timing convergence was consistently acheived.

No abstract available.

In this paper we present techniques shown to significantly enhance the custom circuit design process typical of high-performance microprocessors. This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.

High frequency microprocessor designs require rigorous design guidelines, design methodology advancements, and novel approaches in circuit design style for processors operating in the high megahertz range. Timing closure becomes the single most important design issue, however other design metrics such as area, power and noise need to be given equal consideration within the design cycle. Custom design techniques were used through out the logic circuits and arrays as well as the overall design planning for the 500 MHz microprocessor cycle time.

This paper describes the methodology employed in the design of the G4 S/390 microprocessor. Issues of verifying design metrics of power, noise, timing, and functional correctness are discussed within the context of a performance-driven transistor-level custom design approach. Semi-automated techniques to encourage designer productivity consistent with the objectives of a high-frequency deep submicron design point are presented as are the practical issues associated with managing the complexity of an 8 million transistor design.