Chun Kit Lam

dblp:78/9801 · DBLP profile ↗
← Back
6ranked-venue papers
2as first author
5since 2021 · last 2026
0000-0002-8856-9095ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 4 · 1 first-author · 4 since 2021Systems, architecture and hardware · 3 · 1 first-author · 2 since 2021
YearPublicationVenuePosition
2026 Series-parallel-loop decompositions of control-flow graphs
abstract
Control-flow graphs (CFGs) of structured programs are well known to exhibit strong sparsity properties. Traditionally, this sparsity has been modeled using graph parameters such as treewidth and pathwidth, enabling the development of faster parameterized algorithms for tasks in compiler optimization, model checking, and program analysis. However, these parameters only approximate the structural constraints of CFGs: although every structured CFG has treewidth at most 7, many graphs with treewidth at most 7 cannot arise as CFGs. As a result, existing parameterized techniques are optimized for a substantially broader class of graphs than those encountered in practice. In this work, we introduce a new grammar-based decomposition framework that characterizes exactly the class of control-flow graphs generated by structured programs. Our decomposition is intuitive, mirrors the syntactic structure of programs, and remains fully compatible with the dynamic-programming paradigm of treewidth-based methods. Using this framework, we design improved algorithms for two classical compiler optimization problems: Register Allocation and Lifetime-Optimal Speculative Partial Redundancy Elimination (LOSPRE) . Extensive experimental evaluation demonstrates significant performance improvements over previous state-of-the-art approaches, highlighting the benefits of using decompositions tailored specifically to CFGs.
Xuran Cai, Amir Kafshdar Goharshady, S. Hitarth, Chun Kit Lam
J. Syst. Archit.4
2026 First-Class Constrained Types: Elaboration, Type Inference, Approximation, and a Characterization of Termination
abstract
We study a first-class treatment of constrained types, which were previously confined mostly to ML-style polymorphism. We define System FCCT, an extension of System F with polymorphic subtyping and constraint abstraction in types. A value of type c ⇒ τ can be used at type τ in any context where the subtyping constraint c can be discharged. We show that FCCT exhibits interesting properties. First, all well-typed FCCT terms terminate under call-by-name evaluation (CBN), which can be shown by elaboration into System F. Second, all CBN-terminating terms are well-typed in FCCT. Together, these two properties mean that typability in System FCCT characterizes call-by-name termination. Third, FCCT admits a principal type inference semi-algorithm, called FCCT I , which makes no approximations and can thus be seen as an idealized “ground truth” of type inference. We show that FCCT I indirectly simulates term reduction, shedding some light on the difficulty of bounded polymorphic type inference. Finally, we extend FCCT I to track abstracted call contexts and perform approximation by sharing polymorphic instantiations, ensuring termination on all input terms while preserving soundness. In addition to making the connection between polymorphic subtype constraint solving and term reduction, this paper also establishes a connection between constrained types and existing intersection type systems, which are known to characterize various normalization properties.
Chun Kit Lam, Florent Ferrari, Lionel Parreaux
Proc. ACM Program. Lang.1
2025 Faster Chaitin-like Register Allocation via Grammatical Decompositions of Control-Flow Graphs
abstract
It is well-known that control-flow graphs (CFGs) of structured programs are sparse. This sparsity has been previously formalized in terms of graph parameters such as treewidth and pathwidth and used to design faster parameterized algorithms for numerous compiler optimization, model checking and program analysis tasks.
Xuran Cai, Amir Kafshdar Goharshady, S. Hitarth, Chun Kit Lam
ASPLOS (1)4
2024 Fast and Optimal Extraction for Sparse Equality Graphs
abstract
Equality graphs (e-graphs) are used to compactly represent equivalence classes of terms in symbolic reasoning systems. Beyond their original roots in automated theorem proving, e-graphs have been used in a variety of applications. They have become particularly important as the key ingredient in the popular technique of equality saturation , which has notable applications in compiler optimization, program synthesis, program verification, and symbolic execution, among others. In a typical equality saturation workflow, an e-graph is used to store a large number of equalities that are generated by local rewrites during a saturation phase, after which an optimal term is extracted from the e-graph as the output of the technique. However, despite its crucial role in equality saturation, e-graph extraction has received relatively little attention in the literature, which we seek to start addressing in this paper. Extraction is a challenging problem and is notably known to be NP-hard in general, so current equality saturation tools rely either on slow optimal extraction algorithms based on integer linear programming (ILP) or on heuristics that may not always produce the optimal result. In fact, in this paper, we show that e-graph extraction is hard to approximate within any constant ratio. Thus, any such heuristic will produce wildly suboptimal results in the worst case. Fortunately, we show that the problem becomes tractable when the e-graph is sparse, which is the case in many practical applications. We present a novel parameterized algorithm for extracting optimal terms from e-graphs with low treewidth, a measure of how “tree-like” a graph is, and prove its correctness. We also present an efficient Rust implementation of our algorithm and evaluate it against ILP on a number of benchmarks extracted from the Cranelift benchmark suite, a real-world compiler optimization library based on equality saturation. Our algorithm optimally extracts e-graphs with treewidths of up to 10 in a fraction of the time taken by ILP. These results suggest that our algorithm can be a valuable tool for equality saturation users who need to extract optimal terms from sparse e-graphs.
Amir Kafshdar Goharshady, Chun Kit Lam, Lionel Parreaux
Proc. ACM Program. Lang.2
2023 The Bounded Pathwidth of Control-Flow Graphs
abstract
Pathwidth and treewidth are standard and well-studied graph sparsity parameters which intuitively model the degree to which a given graph resembles a path or a tree, respectively. It is well-known that the control-flow graphs of structured goto-free programs have a tree-like shape and bounded treewidth. This fact has been exploited to design considerably more efficient algorithms for a wide variety of static analysis and compiler optimization problems, such as register allocation, µ-calculus model-checking and parity games, data-flow analysis, cache management, and liftetime-optimal redundancy elimination. However, there is no bound in the literature for thepathwidthof programs, except the general inequality that the pathwidth of a graph is at mostO(lgn) times its treewidth, wherenis the number of vertices of the graph. In this work, we prove that control-flow graphs of structured programs have bounded pathwidth and provide a linear-time algorithm to obtain a path decomposition of small width. Specifically, we establish a bound of 2 ·don the pathwidth of programs with nesting depthd. Since real-world programs have small nesting depth, they also have bounded pathwidth. This is significant for a number of reasons: (i) ‍pathwidth is a strictly stronger parameter than treewidth, i.e. ‍any graph family with bounded pathwidth has bounded treewidth, but the converse does not hold; (ii) ‍any algorithm that is designed with treewidth in mind can be applied to bounded-pathwidth graphs with no change; (iii) ‍there are problems that are fixed-parameter tractable with respect to pathwidth but not treewidth; (iv) ‍verification algorithms that are designed based on treewidth would become significantly faster when using pathwidth as the parameter; and (v) ‍it is easier to design algorithms based on bounded pathwidth since one does not have to consider the often-challenging case of merge nodes in treewidth-based dynamic programming. Thus, we invite the static analysis and compiler optimization communities to adopt pathwidth as their parameter of choice instead of, or in addition to, treewidth. Intuitively, control-flow graphs are not only tree-like, but also path-like and one can obtain simpler and more scalable algorithms by relying on path-likeness instead of tree-likeness. As a motivating example, we provide a simpler and more efficient algorithm for spill-free register allocation using bounded pathwidth instead of treewidth. Our algorithm reduces the runtime fromO(n·r2 ·tw·r+ 2 ·r) toO(n·pw·rpw·r+r+ 1), wherenis the number of lines of code,ris the number of registers,pwis the pathwidth of the control-flow graph andtwis its treewidth. We provide extensive experimental results showing that our approach is applicable to a wide variety of real-world embedded benchmarks from SDCC and obtains runtime improvements of 2-3 orders of magnitude. This is because the pathwidth is equal to the treewidth, or one more, in the overwhelming majority of real-world CFGs and thus our algorithm provides an exponential runtime improvement. As such, the benefits of using pathwidth are not limited to the theoretical side and simplicity in algorithm design, but are also apparent in practice.
Giovanna Kobus Conrado, Amir Kafshdar Goharshady, Chun Kit Lam
Proc. ACM Program. Lang.3
2009 A Class D Amplifier Output Stage with Low THD and High PSRR
abstract
This paper presents a class D amplifier output stage with low total harmonic distortion (THD) and high power supply rejection ratio (PSRR). The class D output stage reduces the non-linearities and supply noise by means of a second-order negative feedback loop embodying a single stage second-order integrator and a Schmitt trigger comparator. Unlike conventional feedback, the reference input signal of the feedback loop is a digital pulse width modulated signal. The feedback loop compensates for any external errors or non-linearities in the output PWM signal by modulating the pulse width of the output signal. Based on simulation using AMS 0.35 mum CMOS process, our proposed closed-loop output stage can achieve a PSRR of .90 dB at 1 kHz and a THD well below 0.05% up to 10 kHz. This shows that negative feedback can effectively be employed to improve the PSRR and THD performance of a class D output stage with digital PWM input.
Chun Kit Lam, Meng Tong Tan
ISCAS1