Multicore CPUs typically share the Last-Level Cache (LLC) across cores, leading to interference between co-executing workloads with significant performance and security implications. Page coloring has emerged as an effective software mechanism for LLC partitioning. Simultaneously, virtual memory enables fundamental abstractions, but incurs increasing performance overheads due to address translation. Huge pages alleviate this issue by expanding TLB reach, thereby reducing TLB misses and the associated costly page table walks. However, these two techniques are considered mutually exclusive, since huge pages span all LLC sets, precluding coloring.In this paper we introduce Colored Huge Pages (CHP), a hardware-software co-design that enables the simultaneous use of page coloring and huge pages. By distributing the physical frames of a virtually contiguous huge page across physical memory in a predictable strided pattern, our design allows coloring of the individual pages while preserving the TLB reach and translation efficiency of conventional huge pages. On the software side, we modify the OS allocator to construct colored huge pages by extracting appropriately colored pages from larger physical blocks and caching leftover mappings for future use. On the hardware side, we extend the L2 TLB to efficiently translate these mappings by leveraging their regular structure. We implement our approach in a recent Linux kernel and evaluate it using memory intensive workloads. CHP mitigates LLC contention and address translation overheads, improving performance by 33.7% compared to using 4 KB pages without LLC partitioning, requiring only minimal OS and architectural modifications. Contrary to prior approaches, our proposal maintains comparable effectiveness under fragmentation, avoids inducing additional cache misses, and incurs only negligible page fault overhead relative to Transparent Huge Pages (THP).

Silent Data Corruption (SDC) is the most severe effect of a silicon defect in a CPU or other computing chip. The arithmetic units of a CPU are, usually, unprotected and are, thus, the ones that most likely produce SDCs (as well as visible malfunctions of programs such as crashes). In this work, we shed light on the traversal of silicon defects from their point of origin deep inside arithmetic units of complex CPUs towards the program result. We employ microarchitecture-level fault injection enhanced with gate-level designs of the arithmetic units of interest. The hybrid setup combines (i) the accuracy of the hardware and fault modeling and (ii) the speed of program simulation to run long programs to end (thus observing SDC incidents); the analysis that this combination delivers is impossible at other abstraction layers which are either hardware-agnostic (software level) or extremely slow (gate-level). We quantify the effects of faults in two stages and with multiple metrics: (a) how faults propagate to the outputs of the arithmetic units when individual instructions are executed, and (b) how faults eventually affect the outcome of the program generating SDCs, crashes, or being masked. Our fine-grain findings can be utilized for informed fault detection and tolerance strategies at the hardware or the software levels.

Hyperscalers have reported unexpectedly high numbers of defective CPU chips, with a defect rate of 1 in a 1000, leading to Silent Data Corruptions (SDCs) in their computing fleets. However, there is no public data on the rate of SDC incidents (corrupted program executions) in large fleets, nor nor any detailed information on which CPU units, microarchitectures, or workloads are more likely to generate SDCs due to silicon defects. While CPU array structures have been studied for fault effects, arithmetic units like integer and floating-point units have not been thoroughly analyzed as potential root causes of SDCs. This paper addresses this critical gap by accurately modeling hardware faults in the arithmetic units of modern x86 CPUs and measuring the probability and rates of SDCs. Using a full-system gem5-based fault injector, the paper examines SDC trends across five recent $x 86$ microarchitectures, various arithmetic units, and instruction classes. By integrating real-world defect rates from large-scale datacenter experiments with early-stage modeling and simulation, the paper provides critical insights into SDC incident rates across different systems. This information is essential for guiding hardware-based or software-based fault protection methods and is the paper’s primary contribution to minimizing the impact of silent data corruptions in computing.

Programmable AI accelerators become increasingly important to modern computing infrastructure, thus, their reliability is critical for the integrity of the produced results. Silent Data Corruptions (SDCs)-incorrect program outputs that occur without any warning or notification-have been reported by hyperscalers such as Meta, Google, and Alibaba, affecting both CPUs and AI chips in production environments. SDCs originate from a range of low-level causes including manufacturing defects, aging-induced degradation, process variation, particle strikes, and electromagnetic interference. In this work, we revisit the modeling debate between software-level and microarchitecture-level fault injection for estimating SDC vulnerability, in the context of programmable AI accelerators. While software-level (hardware agnostic) techniques are fast and easy to deploy, studies on CPUs and GPUs have shown they produce misleading results due to their lack of the hardware notion which determines faults propagation or filtering. We show that these issues also persist dramatically in AI accelerators. Using detailed microarchitectural modeling, we demonstrate that even so-called hardware-aware software-level approaches can misestimate FIT rates by more than 4 × across realistic accelerator configurations. Our findings support microarchitecture-level simulation as the most effective tradeoff point between accuracy and scalability for early-stage reliability analysis of programmable AI hardware.

Cache memory reliability is a critical concern in modern processor architectures, particularly in systems deployed in fault-prone environments or at large scale. As modern computing systems increasingly rely on cache memories for performance, ensuring their reliability against transient faults (soft errors) is crucial. Several protection schemes, such as parity or error-correcting codes (ECC), have been proposed to enhance cache robustness. However, these techniques introduce trade-offs in terms of performance and effectiveness, which are particularly relevant in RISC-V-based CPUs due to their flexibility and modular design. This paper presents a comprehensive characterization and design space exploration of error protection mechanisms (parity and Single Error Correction Double Error Detection - SECDED - ECC) in the cache memories of RISC-V CPUs. We employ statistical fault injection at the microarchitecture level to evaluate the impact of transient faults on system reliability, analyzing their effects across system layers in a full-system setup using the gem5 simulator, the only environment that supports the execution of long workloads. By comparing caches with and without protection, we provide insights into error resilience, overheads, and the effectiveness of protection schemes. Our study can drive the selection of appropriate protection strategies for various RISC- V implementations, ranging from embedded systems to high-performance computing platforms. Our findings offer valuable guidance for the design of robust and efficient RISC- V-based systems operating under reliability constraints.

As semiconductor fabrication scales to smaller technology nodes, process variation has become a significant challenge, affecting power consumption, thermal behavior, and voltage stability in microprocessors and GPUs. Conservative voltage guardbands are traditionally used to ensure reliable operation under worst-case process, voltage, and temperature (PVT) variations, but they lead to excessive power consumption. Reducing the supply voltage, while maintaining a fixed frequency, has emerged as a promising technique for improving energy efficiency without sacrificing computational correctness and performance. While extensive research has been conducted on reducing the voltage levels in CPUs and NVIDIA GPUs, AMD GPUs remain relatively unexplored, particularly in terms of process variation. This variation, inherent in semiconductor manufacturing, results in differences in power efficiency, thermal characteristics, and voltage stability even among identical GPUs from the same production batch. In this paper, we present an extensive study on voltage scaling beyond nominal conditions for three modern AMD NAVI GPUs (i.e., RX 7600 XT, 7700 XT, and 7800 XT) executing both conventional benchmarks and PyTorch-based machine learning workloads. We evaluate and present power savings and execution stability under undervolted conditions, highlighting the impact of chip-to-chip variability. Our findings contribute to a deeper understanding of undervolting in AMD GPUs and its dependence on process variation, providing insights into practical power-saving strategies.

Compute-in-Memory (CiM) employing Non-Volatile Memory (NVM) technology is an emerging paradigm that promises higher power efficiency for important data-intensive computations. The performance, power, and resilience properties of emerging NVM technologies determine the efficiency of architectures built around processors and computational memories, and affect design decisions. Thus, fast exploration of the broad design space is necessary to assist decision-making. We present Sisyphus, the first cross-layer framework built to facilitate computer architecture research when such an exploration is required. Sisyphus incorporates detailed technology information for various CiM circuit designs based on STT-MRAM, ReRAM, and PCM technologies and integrates them in fast microarchitecture level system models in gem5 to evaluate performance, power, and resilience (through fault injection) across a large space of design options. Sisyphus’ holistic modeling enables the comprehensive evaluation of all efficiency aspects during the execution of actual workloads on the CPU-CiM architecture. This allows for comparisons to a baseline CPU-only system. In our experimental evaluation, we demonstrate how Sisyphus can derive conclusions regarding the prevalence of one NVM type over another, depending on the prioritized optimization aspect(s).

Graphics Processing Units (GPUs) are widely de-ployed and utilized across various computing domains including cloud and high-performance computing. Considering its extensive usage and increasing popularity, ensuring GPU reliability is cru-cial. Software-based reliability evaluation methodologies, though fast, often neglect the complex hardware details of modern GPU designs. This oversight could lead to misleading measurements and misguided decisions regarding protection strategies. This paper breaks new ground by conducting an in-depth examination of well-established vulnerability assessment methods for modern GPU architectures, from the microarchitecture all the way to the software layers. It highlights divergences between popular software-based vulnerability evaluation methods and the ground truth cross-layer evaluation, which persist even under strong protections like triple modular redundancy. Accurate evaluation requires considering fault distribution from hardware to software. Our comprehensive measurements offer valuable insights into the accurate assessment of GPU reliability.

In this work, we discuss our vision for neuromorphic accelerators based on integrated photonics within the framework of the Horizon Europe NEUROPULS project. Augmented integrated photonic architectures that leverage phase-change and III-V materials for optical computing will be presented. A CMOS-compatible platform will be discussed that integrates these materials to fabricate photonic neuromorphic architectures, along with a gem5-based simulation platform to model accelerator operation once it is interfaced with a RISC-V processor. This simulation platform enables accurate system-level accelerator modeling and benchmarking in terms of key metrics such as speed, energy consumption, and footprint.

In the contemporary security landscape, the incorporation of photonics has emerged as a transformative force, unlocking a spectrum of possibilities to enhance the resilience and effectiveness of security primitives. This integration represents more than a mere technological augmentation; it signifies a paradigm shift towards innovative approaches capable of delivering security primitives with key properties for low-power systems. This not only augments the robustness of security frameworks, but also paves the way for novel strategies that adapt to the evolving challenges of the digital age. This paper discusses the security layers and related services that will be developed, modeled, and evaluated within the Horizon Europe NEUROPULS project. These layers will exploit novel implementations for security primitives based on physical un-clonable functions (PUFs) using integrated photonics technology. Their objective is to provide a series of services to support the secure operation of a neuromorphic photonic accelerator for edge comnuting applications.

Silent Data Corruptions (SDCs) due to defects in computing chips (CPUs, GPUs, AI accelerators) is a critical threat to the quality of large-scale computing in different application domains: cloud computing, high-performance computing, edge computing. Recent public reports by cloud hyperscalers have emphasized that apart from the usual suspects for SDCs (memory, storage, network), the heart of the computations, the processing elements of all types generate an unexpectedly large rate of SDCs which can cause erroneous calculations and severe information loss. We report, in a consolidated form, recent efforts to correlate early microarchitecture-level simulation-based predictions about the likelihood, rates, severity, and root causes of SDCs and large-scale in-field studies in cloud data centers. Early microarchitecture-level prediction of SDC characteristics (susceptible units, workloads, instructions) can shed light to the cryptic problem of SDCs. The findings of a diligent pre-silicon analysis can assist better understanding of SDCs and can thus drive effective protection decisions either at the hardware or at the software levels at deployment stages.

In this paper, we present gem5-MARVEL, the first consolidated microarchitecture-level fault injection infrastructure for heterogeneous System-on-Chip architectures comprising CPUs of all major Instruction Set Architectures (ISAs) and different types of domain-specific accelerators. The proposed framework is based on a modular design that facilitates flexible fault injection scenarios that correspond to different fault models and system configurations. gem5-MARVEL includes a set of libraries for the automation of fault injection and the analysis of the effects of hardware faults at full system execution. We evaluate the proposed framework on several 64-bit CPU ISAs: x86, Arm, and RISC-V, as well as on different designs of domain-specific accelerators. The case studies we present unveil important insights and demonstrate the effectiveness of the proposed infrastructure in the analysis of the impact of faults on different types of heterogeneous computing systems. gem5-MARVEL facilitates broad design space exploration for entire heterogeneous computing systems at the microarchitecture level, where resilience under realistic fault scenarios can be simultaneously analyzed with performance (the typical use of microarchitectural simulators).

Ensuring the reliability of hardware components is essential, particularly in large-scale installations that demand computing capabilities (cloud data centers, supercomputers, edge systems). Silent data corruptions (SDCs) due to latent defects, manufacturing testing escapes, aging, marginal defects present significant challenges to system integrity and performance. Such silicon defects are often subtle and intermittent, manifesting under specific conditions, thus complicating detection and diagnosis. In this paper, the views of the CPU design powerhouses (Intel, AMD, Arm) that deliver most of the computing power of our days at scale, are summarized. These industry giants share their insights on the challenges posed by SDCs and discuss the strategies and technologies they employ to mitigate these issues.

Several hyperscalers have recently disclosed the occurrence of Silent Data Corruptions (SDCs) in their systems fleets, sparking concerns about the severity of known and the existence of unidentified root causes of faults in CPUs. These incidents reveal that CPU chips have the potential to generate incorrect results for different tasks due to latent manufacturing defects, variability, marginalities, bugs, and aging. To tackle this problem, we present Harpocrates, an automated methodology for the generation of short, constrained-random functional test programs that maximize fault detection in target CPU structures and can be employed at different stages of system lifetime. Harpocrates stands out by adopting a hardware-modelin-the-loop approach, which iteratively refines the generated test programs using a detailed simulation-based microarchitecture engine. The engine models and grades for multiple hardware fault types that can lead to data corruptions during system operation. Harpocrates is versatile and can adapt to various program generators, ISAs, microarchitectures, and fault types. Our results on six important CPU hardware structures show that Harpocrates attains much shorter test generation times than hardware-agnostic publicly available frameworks and outperforms open-source test suites in terms of fault detection capability.

Building on the flexibility of open-source RISC-V-based CPU designs at the register-transfer level (RTL) we deliver a characterization study that is not feasible on commercial CPUs. We identify the major power-consuming hardware structures by focusing on SonicBOOM's out-of-order (OoO) microarchitecture across three design points of increasing aggressiveness. By introducing and employing the SimPoint methodology on a diverse set of workloads, we shed light on the relationship between microarchitecture and energy efficiency of BOOM, which is the highest-performance CPU design in the public domain. Our analysis highlights the Branch Prediction and the Instruction Scheduler Units as the most power-intensive components. We evaluate the energy efficiency (performance per watt) of the three design configurations of BOOM and conclude that the smallest of the three OoO cores, while being the slowest, prevails. The proposed experimental flow can be used to evaluate any CPU design using arbitrarily large workloads due to the effective use of the SimPoint methodology we introduce in Chipyard - in our case offering a 45-fold reduction of simulation time. Our findings, encompassing 8 key takeaways, can assist microprocessor designers in optimizing energy efficiency by addressing major power contributors.

Due to extensive deployment and heavy usage of GPUs, ensuring the reliability of such devices is crucial. Current software-based reliability evaluation methodologies, albeit fast, often neglect the intricate hardware complexities of modern GPU designs. This oversight could result in misleading measurements and misguided decisions regarding protection strategies. This work breaks new ground by examining well-established vulnerability assessment methods for modern GPU architectures, from the microarchitecture all the way to the software layers. It highlights divergences between popular software-based vulnerability evaluation methods and the ground truth cross-layer evaluation (which, as we show, holds even when strong protection like triple modular redundancy is employed); accurate evaluation requires considering fault distribution from hardware to software. Our comprehensive measurements offer valuable insights into accurately assessing GPU reliability.

It is widely accepted that cosmic rays are a plausible cause of DRAM errors in high-performance computing (HPC) systems, and various studies suggest that they could explain some aspects of the observed DRAM error behavior. However, this phenomenon is insufficiently studied in production environments. We analyze the correlations between cosmic rays and DRAM errors on two HPC clusters: a production supercomputer with server-class DDR3-1600 and a prototype with LPDDR3-1600 and no hardware error correction. Our error logs cover 2000 billion MB-hours for the MareNostrum 3 supercomputer and 135 million MB-hours for the Mont-Blanc prototype. Our analysis combines quantitative analysis, formal statistical methods and machine learning. We detect no indications that cosmic rays have any influence on the DRAM errors. To understand whether the findings are specific to systems under study, located at 100 meters above the sea level, the analysis should be repeated on other HPC clusters, especially the ones located on higher altitudes. Also, analysis can (and should) be applied to revisit and extend numerous previous studies which use cosmic rays as a hypothetical explanation for some aspects of the observed DRAM error behaviors.

VITAMIN-V is a 2023–2025 Horizon Europe project that aims to develop a complete RISC-V open-source software stack for cloud services with comparable performance to the cloud-dominant x86 counterpart and a powerful virtual execution environment for software development, validation, verification, and testing that considers the relevant RISC-VISA extensions for cloud deployment. VITAMIN-V will specifically support the RISC-V extensions for virtualization, cryptography, and vec-torization in three virtual environments: QEMU, gem5, and cloud FPGA prototype platforms. The project will focus on European Processor Initiative (EPI) based RISC-V designs and accelerators. VITAMIN-V will also support the ISA extensions by adding the compiler and toolchain support. Furthermore, it will develop novel software validation, verification, and testing approaches to ensure software trustworthiness. To enable the execution of complete cloud stacks, VITAMIN-V will port all necessary machine-dependent modules in relevant open-source cloud software distributions, focusing on three cloud setups. Finally, VITAMIN-V will demonstrate and benchmark these three cloud setups using relevant AI, big-data, and serverless applications. VITAMIN-V aims to match the software performance of its x86 equivalent while contributing to RISC-V open-source virtual environments, software validation, and cloud software suites.

Vitamin-V is a project funded under the Horizon Europe program for the period 2023-2025. The project aims to create a complete open-source software stack for RISC-V that can be used for cloud services. This software stack is intended to have the same level of performance as the x86 architecture, which is currently dominant in the cloud computing industry. In addition, the project aims to create a powerful virtual execution environment that can be used for software development, validation, verification, and testing. The virtual environment will consider the relevant RISC-V ISA extensions required for cloud deployment. Commercial cloud systems use hardware features currently unavailable in RISC-V virtual environments, including virtualization, cryptography, and vectorization. To address this, Vitamin-V will support these features in three virtual environments: QEMU, gem5, and cloud-FPGA prototype platforms. The project will focus on providing support for EPI-based RISC-V designs for both the main CPUs and cloud-important accelerators, such as memory compression. The project will add the compiler (LLVM-based) and toolchain support for the ISA extensions. Moreover, Vitamin-V will develop novel approaches for validating, verifying, and testing software trustworthiness. This paper focuses on the plans and visions that the Vitamin-V project has to support validation, verification, and testing for cloud applications, particularly emphasizing the hardware support that will be provided.

This special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. Our approach aims to develop an augmented silicon photonics platform, an FPGA-powered RISC-V-connected computing platform, and a complete simulation platform to demonstrate the neuromorphic accelerator capabilities. In particular, their main advantages and limitations will be addressed concerning the underpinning technology for each platform. Then, we will discuss three targeted use cases for edge-computing applications: Global National Satellite System (GNSS) anti-jamming, autonomous driving, and anomaly detection in edge devices. Finally, we will address the reliability and security aspects of the stand-alone accelerator implementation and the project use cases.

We propose AVGI, a new Statistical Fault Injection (SFI)-based methodology, which delivers orders of magnitude faster assessment of the Architectural Vulnerability Factor (AVF) of a microprocessor chip, while retaining the high accuracy of SFI. The proposed methodology is based on three key insights about the way that faults traverse complex out-of-order microarchitectures: (1) the distribution of the different ways that hardware faults manifest at the software (i.e., the first effects of faults to the software layer) is relatively uniform across workloads, (2) the final effects of faults in a specific hardware structure (i.e., their effect on the program execution) is relatively uniform for different workloads and depends on the distribution of the above fault manifestations, and (3) the majority of first manifestations occur in certain timeframe from the fault occurrence, which is significantly shorter than the complete execution of the workload, and depends on the type of hardware structure. Based on these insights, the proposed AVGI methodology accurately estimates the complete cross-layer vulnerability (i.e., AVF) for every hardware structure in fine granularity (SDCs and Crashes). Our experimental analysis shows that preserving high levels of accuracy, the proposed AVF assessment methodology is up to 337x and 440x faster than an accelerated exhaustive SFI, for two different microarchitectures of 64-bit Armv8 and 32-bit Armv7 CPU models, respectively.

Silent Data Corruptions (SDCs) pose a significant threat to the integrity of digital systems. These stealthy saboteurs silently corrupt data, remaining undetected by traditional error handling mechanisms. The silent nature of SDCs makes them challenging to trace at the hardware level, as they evade error reporting systems. Instead, their effects manifest at the application level, potentially causing data loss and system-wide issues. Detecting and measuring SDCs present unique challenges. Their low occurrence rates, dependence on hardware structure and software workloads, and correlation to environmental factors make accurate measurement complex. Addressing SDCs requires proactive measures to prevent data corruption and ensure digital integrity. Software redundancy methods provide a means to tolerate SDCs by introducing duplication or triplication of application resources. However, these methods come with their own limitations, including increased code size, altered execution patterns, and potential vulnerability to other types of failures. Understanding the nature of SDCs and developing effective mitigation strategies are crucial for maintaining digital integrity in large-scale infrastructure services. This paper sheds light on the stealthy saboteurs that silently corrupt data, emphasizes the need for comprehensive measurement techniques, and explores the limitations of existing mitigation approaches. By addressing the challenges posed by SDCs, we can fortify digital systems against these hidden threats and ensure the reliability and integrity of our digital infrastructure.

Silent data corruptions (SDCs) pose a significant challenge to the reliable operation of modern microprocessors. As the need for enhanced performance and reliability continues to grow, it becomes essential to gain insight into the potential malfunctions and the occurrence of unnoticeable errors that microprocessors might encounter across different Instruction Set Architectures (ISAs) and microarchitectures. This study delves into assessing failures and rates of silent data corruptions within CPUs, shedding light on the variables that impact these rates and their consequences on system dependability. In this context, we present a comprehensive comparative investigation of SDC susceptibilities in CPU hardware structures, mainly targeting the L1 data cache, L1 instruction cache, physical register file, and a modern CPU's primary functional units (FUs). We carry out this investigation across three prominent CPU architectures: x86, Arm, and RISC-V. Our aim is to analyze both transient and permanent faults to evaluate the susceptibility of these architectures to SDCs.

Microprocessor power consumption and dependability are both crucial challenges that designers have to cope with due to shrinking feature sizes and increasing transistor counts in a single chip. These two challenges are mutually destructive: microprocessor reliability deteriorates at lower supply voltages that save power. An important dependability metric for microprocessors is their radiation-induced soft error rate (SER). This work goes beyond state-of-the-art by assessing the trade-offs between voltage scaling and soft error rate (SER) on a microprocessor system executing workloads on real hardware and a full software stack setup. We analyze data from accelerated neutron radiation testing for nominal and reduced microprocessor operating voltages. We perform our experiments on a 64-bit Armv8 multicore microprocessor built on 28 nm process technology. We show that the SER of SRAM arrays can increase up to 40.4% when the device operates at reduced supply voltage levels. To put our findings into context, we also estimate the radiation-induced Failures in Time (FIT) rate of various workloads for all the studied voltage levels. Our results show that the total and the Silent Data Corruptions (SDC) FIT of the microprocessor operating at voltage-scaled conditions can be 6.6 × and 16 × larger than at the nominal voltage, respectively. Moreover, changes in the microprocessor’s clock frequency do not have a noticeable impact on its soft error susceptibility. The findings of this work can aid computer architects in striking a balance between power and dependability, thus, designing more robust and efficient microprocessors.

Chip manufacturers and hyperscalers are becoming increasingly aware of the problem posed by Silent Data Errors (SDE) and are taking steps to address it. Major computing facilities operators like Meta and Google have emphasized the critical role of SDEs in today’s microprocessors. Numerous studies in the literature have highlighted the severity of this issue, especially in datacenter applications operating at large scales. These errors can lead to data loss and require a significant amount of time and effort to resolve through debugging engineering efforts, which can take months to complete. In this paper, we provide an overview of the issue of SDEs, including an explanation of the problem and the current methods used to address it, as well as gaps that still exist in addressing the issue. We also discuss the different sources of SDEs, including post-manufacturing testing failures, voltage and timing marginalities, and hard-to-detect faults. The paper emphasizes the impact of timing marginalities as a significant source of SDEs. Finally, our spotlight points to the architecture and system dimensions of the problem: we describe the challenges of measuring the true (still unknown) rates of SDE from CPUs, and emphasize on the role of detailed microarchitectural simulation models for this purpose. We present data on the severity of SDEs and their predicted rates under various operating conditions, sources of faults, and technology fabrication nodes.

Today more than ever before, academia, manufacturers, and hyperscalers acknowledge the major challenge of silent data corruptions (SDCs) and aim on solutions to minimize its impact by avoiding, detecting, and mitigating SDCs. Recent studies on large scale datacenters conducted by Meta and Google report an unexpected rate of silent data corruption incidents that are attributed to modern microprocessor generations. Despite the acknowledged severity of the phenomenon, particularly at the datacenter scale, there is no in-depth analysis of the microarchitectural locations in a complex microprocessor that are more likely to generate an SDC at the program outputs. In this paper, we present a detailed analysis of the faulty behavior of many critical microarchitectural structures of a modern out-of-order microprocessor generating silent data corruptions. Our analysis unveils several observations, including: (i) the magnitude of silent data corruptions attributed to different hardware structures, (ii) the instruction-related parameters that are more likely to result in a silent data corruption, (iii) the extent to which the operating system affects the silent data corruption occurrences, and (iv) the byte positions of a word which are more likely to result in silent data corruptions. Collectively, such findings can assist decisions for hardware and software schemes for the reduction of the likelihood of silent data corruptions generation.

Pre-silicon reliability evaluation of processors is usually performed at the microarchitecture or at the software level. Recent studies on CPUs have, however, shown that software level approaches can mislead the soft error vulnerability assessment process and drive designers towards wrong error protection decisions. To avoid such pitfalls in the GPUs domain, the availability of microarchitecture level reliability assessment tools is of paramount importance. Although there are several publicly available frameworks for the reliability assessment of GPUs, they only operate at the software level, and do not consider the microarchitecture. This paper aims at accurate microarchitecture level GPU soft error vulnerability assessment. We introduce gpuFI-4: a detailed microarchitecture-level fault injection framework to assess the cross-layer vulnerability of hardware structures and entire GPU chips for single and multiple bit faults, built on top of the state-of-the-art simulator GPGPU-Sim 4.0. We employ gpuFI-4 for fault injection of soft errors on CUDA-enabled Nvidia GPU architectures. The target hardware structures that our framework analyzes are the register file, the shared memory, the LI data and texture caches and the L2 cache, altogether accounting for tens of MBs of on-chip GPU storage. We showcase the features of the tool reporting the vulnerability of three Nvidia GPU chip models: two different modem GPU architectures – RTX 2060 (Turing) and Quadro GV100 (Volta) – and an older generation – GTX Titan (Kepler), for both single-bit and triple-bit fault injections and for twelve different CUDA benchmarks that are simulated on the actual physical instruction set (SASS). Our experiments report the Architectural Vulnerability Factor (AVF) of the GPU chips (which can be only measured at the microarchitecture level) as well as their predicted Failures in Time (FIT) rate when technology information is incorporated in the assessment.

In this paper, we propose a cost-effective microarchitectural technique capable of Instantaneously Detecting the Leakage and Duplication (IDLD) of the physical register identifiers used for register renaming in modern out-of-order processor cores. Leakage occurs when a physical register identifier disappears, whereas duplication occurs when the physical register identifier appears twice throughout the renaming logic. IDLD checks each cycle that a code calculated by xoring the physical register identifiers read from and written to arrays, used for managing physical registers allocation, renaming and reclamation, is zero. This invariance is intrinsic to the register renaming subsystem functionality and allows detecting an identifier leakage and duplication instantaneously. Detection of bugs in the complex register renaming subsystem is challenging, since: (a) its operation is not directly observable in program or architectural visible locations, (b) it lies in time-critical paths in the heart of every modern out-of-order core, and (c) it is often the target for optimizations in new core designs, and thus, more susceptible to bugs than legacy subsystems. We demonstrate that bugs in the renaming logic can be very difficult to root cause because, for numerous cases, it takes excessive time, e.g., millions of cycles, for a duplication or leakage to become an architecturally observable error. Even worse, activations of such bugs, depending on microarchitectural state, are often masked by subsequent hardware operations. Hence, an activation of a rarely occurring leakage or duplication bug during post-silicon validation can go undetected and escape in the field. The difficulty of root-causing register identifier duplication and leakage without IDLD is demonstrated using detailed bug modeling at the microarchitecture level, whereas the low overhead of IDLD is confirmed using RTL design analysis.

Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear to which extend fault injection can provide an accurate error rate estimation at early stages and if beam experiments can be used to identify the weakest resources in a device. The importance and challenges associated with a timely, but yet realistic reliability evaluation grow with the increase of complexity in both the hardware domain, with the integration of different types of cores in an SoC (System-on-Chip), and the software domain, with the OS (operating system) required to take full advantage of the available resources. In this paper, we combine and analyze data gathered with extensive beam experiments (on thefinalphysical CPU hardware) and microarchitectural fault injections (onearlymicroarchitectural CPU models). We target a standalone Arm Cortex-A5 CPU and an Arm Cortex-A9 CPU integrated into an SoC and evaluate their reliability in bare-metal and Linux-based configurations. Combining experimental data that covers more than 18 million years of device time with the result of more than 176,000 injections we find that both the SoC integration and the presence of the OS increase the system DUEs (Detected Unrecoverable Errors) rate (for different reasons) but do not significantly impact the SDCs (Silent Data Corruptions) rate which is solely attributed to the CPU core. Our reliability analysis demonstrates that even considering SoC integration and OS inclusion, early, pre-silicon microarchitecture-level fault injection delivers accurate SDC rates estimations and lower bounds for the DUE rates.

CPUs typically operate at a voltage which is higher than what is strictly required, using voltage margins to account for process variability and anticipate any combination of adverse operating conditions. However, these worst-case scenarios occur rarely, if ever, thus the operating voltage is overly pessimistic resulting in excessive power dissipation which leads to decreased performance under power capping. In this paper, we investigate the impact of reducing voltage margins beyond the nominal level on the efficiency of CPU power capping mechanisms, for three commercial systems, two Applied Micro ARMv8 micro-servers (X-Gene2 and X-Gene3) and an Intel x86-64 (Xeon E3). We show that CPU power capping at reduced voltage margins compared with Intel’s RAPL and Dynamic Frequency Scaling (DFS) mechanisms results in performance improvement by up to 64 and 24 percent on average, respectively. In combination with state-of-the-art thread packing, the reduction of CPU voltage margins results in 36, 33 and 27 percent performance improvement compared with RAPL and DFS for the Xeon E3 and the X-Gene processors, respectively. Also, we validate the robustness of our approach with a set of long-running experiments and show that significant energy gains can be achieved even when considering the cost of checkpointing and recovery in large-scale systems.

We are witnessing an explosive growth in the number of Internet-connected devices and the emergence of several new classes of Internet of Things (IoT) applications that require rapid processing of an abundance of data. To overcome the resulting need for more network bandwidth and low network latency, a new paradigm has emerged that promotes the offering of Cloud services at the Edge, closer to users. However, the Edge is a highly constrained environment with limited power budget for servers per Edge installation which, in turn, limits the number of Internet-connected devices, such as sensors, that an installation can service. Consequently, the limited number of sensors leads to a reduction in the area coverage provided by them and puts in question the effectiveness for deploying IoT applications at the Edge. In this paper, we investigate the benefits of running an emerging security focused IoT application, (jamming detection), at the Edge vs. the Cloud by developing a Total Cost of Ownership (TCO) model, which considers the application's requirements as well as the Edge's constraints. For the first time, we build such a model based on realistic performance and energy-efficiency measurements obtained from commodity 64-bit ARM based micro-servers that are excellent candidates for supporting Cloud services at the Edge. Such servers represent the type of devices that can provide the right balance between power and performance, without requiring any complicate cooling and power supply infrastructure, which will not be available at the de-centralized deployments. Aiming at improving the energy efficiency, we exploit the pessimistic design margins adopted conventionally in such devices and investigate their operation under lower than nominal supply voltage and memory refresh-rate. Our results show that the jamming detection application deployed at an Edge environment is superior to a Cloud based solution by up to 2.13 times in terms of TCO. Moreover, when servers operate below nominal conditions, we can achieve up to 9 percent power savings which enables in several situations 100 percent gains in the TCO/area-coverage metric, i.e double area can be served with the same TCO.

In this paper, we revisit the system vulnerability stack for transient faults. We reveal severe pitfalls in widely used vulnerability measurement approaches, which separate the hardware and the software layers. We rely on microarchitecture level fault injection to derive very tight full-system vulnerability measurements. For our architectural and microarchitectural measurements, we employ GeFIN, a state-of-the-art fault injector built on top of the gem5 simulator, while for software level measurements we employ the LLFI fault injector. Analyzing two different Arm ISAs and two different microarchitectures for each ISA, we quantify the sources and the magnitude of error of architecture and software level vulnerability evaluation methods, which aim to reproduce the effects of hardware faults. We show that widely applied methodologies for system resilience evaluation fail to capture important fault manifestation and propagation aspects and lead to misleading findings, which report opposite vulnerability results than a comprehensive cross-layer analysis. To justify the validity of our findings we employ a state-of-the-art software-based fault tolerance technique and evaluate its impact at all layers through a case study. Our evaluation shows that although higher-level methods can report significant vulnerability improvements (up to 3.8x vulnerability reduction), the actual cross-layer vulnerability of the protected system can be degraded (increased) by up to 30% for the selected benchmarks. Our analysis firmly suggests that only accurate methodologies for full-system vulnerability evaluation of a microprocessor can guide informed transient faults protection decisions either at the hardware or at the software layer.

Arm CPU architectures, thanks to their efficiency and flexibility, have been widely adopted in portable user devices such as smartphones, tablets, and laptops. Recently, the high computing efficiency, together with the unique possibility that Arm offers to adapt the architecture for a specific application, pushed the adoption of Arm-based systems both in HPC (High Performance Computing) applications and autonomous vehicles. The possibility of modifying Arm architecture can potentially be extremely beneficial, as selective fault tolerance solutions can be added at the microarchitectural level. The current trend in the design of computing devices is to integrate several functionalities on the same SoC (System-On-Chip). Modern SoCs usually integrate (one or more) CPUs and (one or more) accelerators, such as GPUs (Graphics Processing Units) or FPGAs (Field Programmable Gate Arrays). These SoCs typically allow the computing cores to share common memories, which significantly improves the performance and reduces the total power consumption but may impact the system's reliability. In this work, we have evaluated the impact of SoC integration and OS deployment using beam experiments and microarchitectural fault injection.

Modern microprocessors suffer from increased error rates that come along with fabrication technology scaling. Processor designs continuously become more prone to hardware faults that lead to execution errors and system failures, which raise the requirement of protection mechanisms. However, error mitigation strategies have to be applied diligently, as they impose significant power, area, and performance overheads. Early and accurate reliability estimation of a microprocessor design is essential in order to determine the most vulnerable hardware structures and the most efficient protection schemes. One of the most commonly used techniques for reliability estimation is Architecturally Correct Execution (ACE) analysis.ACE analysis can be applied at different abstraction models, including microarchitecture and RTL and often requires a single or few simulations to report the Architectural Vulnerability Factor (AVF) of the processor structures. However, ACE analysis overestimates the vulnerability of structures because of its pessimistic, worst-case nature. Moreover, it only delivers coarse-grain vulnerability reports and no details about the expected result of hardware faults (silent data corruptions, crashes). In this paper, we present reverse ACE (rACE), a methodology that (a) improves the accuracy of ACE analysis and (b) delivers fine-grain error outcome reports. Using a reverse-order tracing flow, rACE analysis associates portions of the simulated execution of a program with the actual output and the control flow, delivering finer accuracy and results classification. Our findings show that rACE reports an average 1.45X overestimation, compared to Statistical Fault Injection, for different sizes of the register file of an out-of-order CPU core (executing both ARM and x86 binaries), when a baseline ACE analysis reports 2.3X overestimation and even refined versions of ACE analysis report an average of 1.8X overestimation.

Fault injection in early microarchitecture-level simulation CPU models and beam experiments on the final physical CPU chip are two established methodologies to access the soft error reliability of a microprocessor at different stages of its design flow. Beam experiments, on one hand, estimate the devices expected soft error rate in realistic physical conditions by exposing it to accelerated particles fluxes. Fault injection in microarchitectural models of the processor, on the other hand, provides deep insights on faults propagation through the entire system stack, including the operating system. Combining beam experiments and fault injection data can deliver deep insights about the devices expected reliability when deployed in the field. However, it is yet largely unclear if the fault injection error rates can be compared to those reported by beam experiments and how this comparison can lead to informed soft error protection decisions in early stages of the system design. In this paper, we present and analyze data gathered with extensive beam experiments (on physical CPU hardware) and microarchitectural fault injections (on an equivalent CPU model on Gem5) performed with 13 different benchmarks executed on top of Linux on an ARM Cortex-A9 microprocessor. We combine experimental data that cover more than 2.9 million years of natural exposure with the result of more than 80,000 injections. We then compare the soft error rate estimations that are based on neutron beam and fault injection experiments. We show that, for most benchmarks, fault injection can be very accurately used to predict the Silent Data Corruptions (SDCs) rate and the Application Crash rate. The System Crash rate measured with beam experiments, however is much larger than the one estimated by fault injection due to unknown proprietary parts of the physical hardware platform that can't be modeled in the simulator. Overall, our analysis shows that the relative difference between the total error rates of the beam experiments and the fault injection experiments is limited within a narrow range of values and is always smaller than one order of magnitude. This narrow range of the expected failure rate of the CPU provides invaluable assistance to the designers in making effective soft error protection decisions in early design stages.

Energy efficiency is a known major concern for computing system designers. Significant effort is devoted to power optimization of modern systems, especially in large-scale installations such as data centers, in which both high performance and energy efficiency are important. Power optimization can be achieved through different approaches, several of which focus on adaptive voltage regulation. In this paper, we present a comprehensive exploration of how two server-grade systems behave in different frequency and core allocation configurations beyond nominal voltage operation. Our analysis, which is built on top of two state-of-the-art ARMv8 microprocessor chips (Applied Micro's X-Gene 2 and X-Gene 3) aims (1) to identify the best performance per watt operation points when the servers are operating in various voltage/frequency combinations, (2) to reveal how and why the different core allocation options on the available cores of the microprocessor affect the energy consumption, and (3) to enhance the default Linux scheduler to take task allocation decisions for balanced performance and energy efficiency. Our findings, on actual servers' hardware, have been integrated into a lightweight online monitoring daemon which decides the optimal combination of voltage, core allocation, and clock frequency to achieve higher energy efficiency. Our approach reduces on average the energy by 25.2% on X-Gene 2, and 22.3% on X-Gene 3, with a minimal performance penalty of 3.2% on X-Gene 2 and 2.5% on X-Gene 3, compared to the default system configuration.

Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of the most efficient methods to reduce power consumption of a chip. With the galloping adoption of hardware accelerators (i.e., GPUs and FPGAs) in large datacenters and other large-scale computing infrastructures, a comprehensive evaluation of the safe voltage reduction levels for each different chip can be employed for efficient reduction of the total power. We present a survey of recent studies in voltage margins reduction at the system level for modern CPUs, GPUs and FPGAs. The pessimistic voltage guardbands inserted by the silicon vendors can be exploited in all devices for significant power savings. Voltage reduction can reach 12% in multicore CPUs, 20% in manycore GPUs and 39% in FPGAs.

Branch prediction units are key performance components in modern microprocessors as they are widely used to address control hazards and minimize misprediction stalls. The continuous urge of high performance has led designers to integrate highly sophisticated predictors with complex prediction algorithms and large storage requirements. As a result, BPUs in modern microprocessors consume large amounts of power. But when a system is under a limited power budget, critical decisions are required in order to achieve an equilibrium point between the BPU and the rest of the microprocessor. In this work, we present a comprehensive analysis of the effects of low voltage configuration Branch Prediction Units (BPU). We propose a design with separate voltage domain for the BPU, which exploits the speculative nature of the BPU (which is self-correcting) that allows reduction of power without affecting functional correctness. Our study explores how several branch predictor implementations behave when aggressively undervolted, the performance impact of BTB as well as in which cases it is more efficient to reduce the BP and BTB size instead of undervolting. We also show that protection of BPU SRAM arrays has limited potential to further increase the energy savings, showcasing a realistic protection implementation. Our results show that BPU undervolting can result in power savings up to 69%, while the microprocessor energy savings can be up to 12%, before the penalty of the performance degradation overcomes the benefits of low voltage. Neither smaller predictor sizes nor protection mechanisms can further improve energy consumption.

Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal in the presence of single bit upsets caused by radiation induced soft errors. Each system under analysis executes different software workloads both from benchmark suites and from real applications.

The explosive growth of Internet-connected devices will soon result in a flood of generated data, which will increase the demand for network bandwidth as well as compute power to process the generated data. Consequently, there is a need for more energy efficient servers to empower traditional centralized Cloud data-centers as well as emerging decentralized data-centers at the Edges of the Cloud. In this paper, we present our approach, which aims at developing a new class of micro-servers - the UniServer - that exceed the conservative energy and performance scaling boundaries by introducing novel mechanisms at all layers of the design stack. The main idea lies on the realization of the intrinsic hardware heterogeneity and the development of mechanisms that will automatically expose the unique varying capabilities of each hardware. Low overhead schemes are employed to monitor and predict the hardware behavior and report it to the system software. The system software including a virtualization and resource management layer is responsible for optimizing the system operation in terms of energy or performance, while guaranteeing non-disruptive operation under the extended operating points. Our characterization results on a 64-bit ARMv8 micro-server in 28nm process reveal large voltage margins in terms of Vmin variation among the 8 cores of the CPU chip, among three different sigma chips, and among different benchmarks with the potential to obtain up-to 38.8% energy savings. Similarly, DRAM characterizations show that refresh rate and voltage can be relaxed by 35x and 5%, respectively, leading to 23.2% power savings on average.

Branch predictors are widely used to boost the performance of microprocessors. However, this comes at the expense of power because accurate branch prediction requires simultaneous access to several large tables on every fetch. Consumed power can be drastically reduced by operating the predictor under sub-nomimal voltage levels (undervolting) using a separate voltage domain. Faulty behavior resulting from undervolting the predictor arrays impacts performance due to additional mispredictions but does not compromise system reliability or functional correctness. In this work, we explore how two well established branch predictors (Tournament and L-Tage) behave when aggressively undervolted below minimum fault-free supply voltage (Vmin). Our results based on fault injection and performance simulations show that both predictors significantly reduce their power consumption by more than 63% and can deliver a peak 6.4% energy savings in the overall system, without observable performance degradation. However, energy consumption can increase for both predictors due to extra mispredictions, if undervolting becomes too aggressive.

Error monitoring is a critical procedure for most computing systems, varying from HPC to embedded systems domains. Several generic architectures have been proposed and employed in modern processors, offering the capability of hardware-level error detection. This critical information is required to isolate and/or mitigate failures. However, research has revealed many cases where indications of upcoming failures can be identified early and before the actual fail occurrence, known as symptoms. Such cases become more frequent as technology trends try to exploit the conservative worst-case voltage guardbands and push computing systems towards more aggressive and often hazardous regions. In this paper we present HealthLog monitor, a flexible system monitoring service that offers a generic abstraction layer to combine both error and symptom monitoring. HealthLog is capable of monitoring hardware measurements (performance, sensor and errors) as well as external health-related data, allowing combined symptom description and reaction features supported by an API. The scope of the monitor is to offer a universal standard for error reporting and system monitoring mechanisms in all system layers. The current version of HealthLog was developed and tested on AppliedMicro's X-Gene 2 micro-server, but it is a cross-platform solution as it does not depend on a specific architecture. This work demonstrates how platform events, software metrics and external peripheral mechanisms can be combined to deliver early warnings of upcoming failures and trigger evading reactions.

In this paper, we propose the employment of fast targeted programs (diagnostic micro-viruses) that aim to stress individually the main hardware components of a multicore CPU architecture which most likely determine the limits of voltage scaling, i.e. safe Vmin values. We describe in detail the complex development process for the diagnostic micro-viruses and their comprehensive validation in modern multicore CPU hardware. The combined execution of the micro-viruses takes very short time compared to regular programs execution, and can quickly reveal the voltage limits of the cores and chips at voltage levels below nominal. The micro-virus based characterization flow requires orders of magnitude shorter time while it delivers virtually identical: (a) Vmin values for the different CPU chips, and (b) Vmin values for the different cores within a CPU chip. We evaluate our micro-viruses based characterization flow (and compare it to the SPEC-based flow) on three different chips (a nominal graded and two corner parts) of Applied Micro's X-Gene 2 micro-server family (with 8-core ARMv8-based CPUs manufactured in 28nm). We report detailed validation and evaluation results that prove the effectiveness of the micro-viruses for the fast and accurate identification of the voltage margins variability among the chips and the cores of a multicore CPU.

State-of-the-art GPU chips are designed to deliver extreme throughput for graphics as well as for data-parallel general purpose computing workloads (GPGPU computing). Unlike computing for graphics, GPGPU computing requires highly reliable operations. Since provisioning for high reliability may affect performance, the design of GPGPU systems requires the vulnerability of GPU workloads to soft-errors to be jointly evaluated with the performance of GPU chips. We present an extended study based on a consolidated workflow for the evaluation of the reliability in correlation with the performance of four GPU architectures and corresponding chips: AMD Southern Islands and NVIDIA G80/GT200/Fermi. We obtained reliability measurements (AVF and FIT) employing both fault injection and ACE-analysis based on microarchitecture-level simulators. Apart from the reliability-only and performance-only measurements, we propose combined metrics for performance and reliability that assist comparisons for the same application among GPU chips of different ISAs and vendors, as well as among benchmarks on the same GPU chip.

In this paper, we explore the pessimistic voltage guardbands of two multicore x86-64 microprocessor chips that belong to different microarchitectures (one ultra-low power and one high-performance microprocessor), when programs are executed on individual cores of the CPU chips. We also examine the energy and temperature gains as positive effects of lowering the voltage in both chips while preserving the functional correctness of programs. The behavior of the cores was examined executing 8 different workloads from the SPEC CPU2006 suite. Our differential experimental study is performed on two state-of-the-art x86-64 microprocessors: an ultra-low power Intel Core i5-4200U and a high-performance Intel Core i7-3970X. Based on the results, the cores on each microprocessor chip behave differently for different workloads when undervolted, and the voltage guardbands are more than 15% below the nominal voltage levels. We show that the energy efficiency can be increased by a maximum of 20% and the reduction of temperature can be up to 25%.

General Purpose computing on Graphics Processing Unit offers a remarkable speedup for data parallel workloads, leveraging GPUs computational power. However, differently from graphic computing, it requires highly reliable operation in several application domains. In this paper we present SIFI a reliability evaluation framework for soft-errors on AMD GPUs built on top of Multi2Sim, a micro-architectural level simulator. SIFI is capable of computing different reliability metrics by means of two different techniques: fault injection and ACE analysis. Experiments performed on a set of 14 GPGPU applications targeting the AMD Southern Islands GPU architecture show the capability of the tool and the potential of its use to support decisions about the best architectural parameters for a given application.

Early reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural structures modeled in performance simulators is an accurate method to measure their Architectural Vulnerability Factor (AVF) but requires excessively long campaigns to obtain high statistical significance.

State-of-the-art GPU chips are designed to deliver extreme throughput for graphics as well as for data-parallel general purpose computing workloads (GPGPU computing). Unlike graphics computing, GPGPU computing requires highly reliable operation. The performance-oriented design of GPUs requires to jointly evaluate the vulnerability of GPU workloads to soft-errors with the performance of GPU chips. We briefly present a summary of the findings of an extensive study aiming at the evaluation of the reliability of four GPU architectures and corresponding chips, orrelating them with the performance of the workloads.

In this paper, we present the first automated system-level analysis of multicore CPUs based on ARMv8 64-bit architecture (8-core, 28nm X-Gene 2 micro-server by AppliedMicro) when pushed to operate in scaled voltage conditions. We report detailed system-level effects including SDCs, corrected/uncorrected errors and application/system crashes. Our study reveals large voltage margins (that can be harnessed for energy savings) and also large Vmin variation among the 8 cores of the CPU chip, among 3 different chips (a nominal rated and two sigma chips), and among different benchmarks.

Technology evolution has raised serious reliability considerations, as transistor dimensions shrink and modern microprocessors become denser and more vulnerable to faults. Reliability studies have proposed a plethora of methodologies for assessing system vulnerability which, however, highly rely on traditional reliability metrics that solely express failure rate over time. Although Failures In Time (FIT) is a very strong and representative reliability metric, it may fail to offer an objective comparison of highly diverse systems, such as CPUs against GPUs or other accelerators that are often employed to execute the same algorithms implemented for these platforms. In this paper, we propose a reliability evaluation methodology that takes into account the probability of a workload execution failure in order to compare heterogeneous systems, while we also capture the differences in the performance of these systems. We demonstrate the usefulness of the methodology with a test case scenario that compares the reliability and performance of three different commercial CPUs (different ISAs and microarchitectures) and one GPU. We use statistical fault injection to assess the vulnerability of the register file for the four computing systems of our study. The evaluation was performed using a comprehensive set of benchmarks with the same algorithms implemented for each individual system (serial code for the CPUs and parallel code for the GPU). Our findings show that, even though the GPU proves to be three orders of magnitude more vulnerable than CPUs using traditional reliability metrics, our performance-aware evaluation methodology shrinks this gap by 1-2 orders of magnitude providing more informative and realistic measurements to guide designers or programmers decisions.

Post-silicon validation is one of the most important parts of the microprocessor prototype chip lifecycle. It is the last chance for debug engineers to detect defects and bugs that escaped pre-silicon verification, before the chip is released to the market. Effective solutions are required to harness the peak performance of the hardware prototype and evaluate whether the microprocessor chip is fully compliant with the instruction set and other specifications. We perform a comprehensive experimental study on a state-of-the-art microarchitecture to assess and identify the most difficult bugs in address translation caching arrays (multi-level TLBs and MMU Caches), and explain why these bugs persist across generations. We also categorize them into distinct bug scenarios. We then propose a novel methodology for generating random self-checking stimuli programs, which expose and detect such bug scenarios. Our experimental results show that the proposed method can detect difficult bugs that are likely to be missed by traditional post-silicon validation techniques.

Post-silicon validation complements traditional simulation-based pre-silicon verification and offers very high throughput since validation programs run at the speed of the actual hardware. Detection of bugs in the address translation subsystem of a microprocessor is much less straightforward than other hardware blocks because the address translation is an implicit process, which does not have an easily observable output to architecture or program visible locations. Validation of the correctness of the address translation mechanisms (ATMs) of microprocessors is both very important and challenging problem. In this paper, we present an ISA-independent methodology for the post-silicon validation of the ATMs in modern microprocessors. We first capture the effects of design bugs in address translation, by presenting actual bugs scenarios reported for commercial chips. We also describe an effective method for the detection of bugs in all address translation hardware blocks. The validation programs of the method are self-checking, i.e. do not require a bug-free model to compare with. Our experimental evaluation on Gem5 simulator shows the effectiveness of the methodology in detecting bugs in the address translation hardware of an x86-64 microprocessor model.

This paper describes the joint effort of the two FP7 EU projects CLERECO and MoRV toward the definition of an extended reliability information exchange format able to manage reliability information for the full system stack, from technology up to the software level. The paper starts from the RIIF language initiative, proposing a set of new features to improve the expression power of the language and to extend it to the software layer of a system. The proposed extended reliability information exchange format named RIIF-2 has the potential to support the development of next generation reliability analysis tools that will help to fully include reliability evaluation into an automated design flow, pushing cross-layer reliability considerations at the same level of importance as area, timing and power consumption when performing design exploration for new products.

The increasing density and complexity of modern microprocessors, which is driven by manufacturing technologies scaling, significantly affect their reliability. Reliability evaluation during the early design stages is a challenging process for microprocessor designers. Statistical fault-injection on microarchitecture simulators is commonly used, among other techniques, since it can deliver early and accurate reliability estimations for many important microprocessor hardware structures. However, full-system microarchitectural simulators have a relatively small simulation throughput. Thus, the number of injection experiments that can be performed during a fault injection campaign can be limited and therefore lead to smaller statistical significance of the reliability assessment. Aiming to boost the throughput of microarchitecture-level fault injection, we present, in this paper, a multi-faceted microarchitecture-level toolset for reliability assessment of modern microprocessors. The framework is built around the Gem5 simulator and provides several modes of operation which employ acceleration features for all stages of a fault-injection based reliability assessment campaign. The tool throughput and the accuracy of the delivered reliability assessments can be traded off and allow architects to make informed decisions about the most suitable error protection mechanisms of any given microarchitecture and workload by studying the reports delivered by the toolset. We provide experimental results of the different modes of the toolset for both the x86 and ARM out-of-order models of Gem5. Our experimental results show that up to 8x acceleration of the fault injection campaigns can be achieved with less than 0.5 percentile points of accuracy loss.

Modern many-core Graphics Processing Units (GPUs) are extensively employed in general purpose computing (GPGPU), offering a remarkable execution speedup to inherently data parallel workloads. Unlike graphics computing, GPGPU computing has more stringent reliability requirements. Thus, accurate reliability assessment of GPU hardware structures is important for making informed decisions for error protection. In this paper we focus on microarchitecture-level reliability assessment for GPU architectures. The paper makes the following contributions. First, it presents a comprehensive fault injection framework that targets key hardware structures of GPU architectures such as the register file, the shared memory, the SIMT stack and the instruction buffer, which altogether occupy large part of a modern GPU silicon area. Second, it reports our reliability assessment findings for the target structures, when the GPU executes a diverse set of twelve GPGPU applications. Third, it discusses remarkable differences in the results of fault injection when the applications are simulated in the virtual NVIDIA GPUs instruction set (ptx) vs. the actual instruction set (sass). Finally, it discusses how the framework can be employed either by architects in the early stages of design phase or by programmers for a GPU application's error resilience enhancement.

System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.

High-performance microprocessors employ data prefetchers to mitigate the ever-growing gap between CPU computing rates and memory latency. Technology scaling along with low voltage operation exacerbates the likelihood and rate of hard (permanent) faults in technologies used by prefetchers such as SRAM and flip flop arrays. Faulty prefetch behavior does not affect correctness but can be detrimental to performance. Hard faults in data prefetchers (unlike their soft counterparts which are rare) can cause significant single-thread performance degradation and lead to large performance variability across otherwise identical cores. In this paper, we characterize in-depth both of these aspects in microprocessors suffering from multiple hard faults in their data prefetcher components. Our study reveals fault scenarios in the prefetcher table that can degrade IPC by more than 17%, while faults in the prefetch input and request queues can slow IPC up to 24% and 26%, respectively, compared to fault-free operation. Moreover, we find that a faulty data prefetcher can substantially increase the performance variability across identical cores: the standard deviation of IPC loss for different benchmarks can be more than 4.5%.

Early decisions in microprocessor design require a careful consideration of the corresponding performance and reliability implications of transient faults. The size and organization of important on-chip hardware components such as caches, register files and buffers have a direct impact on both the microprocessor resilience to soft errors and the execution time of the applications. In this paper, we employ a state-of-the-art x86-64 full-system micro-architectural simulator and a comprehensive fault injection framework built on top of it to deliver a detailed evaluation of the reliability and performance tradeoffs for major hardware components across several important parameters of their design (size, associativity, write policy, etc.). We also propose a simple and flexible fitness function that measures the aggregate effect of such design changes on the reliability and the performance of the studied workload.

Nowadays, the scientific community is looking for ways to understand the effect of software execution on the reliability of a complex system when the hardware layer is unreliable. This paper proposes a statistical reliability analysis model able to estimate system reliability considering both the hardware and the software layer of a system. Bayesian Networks are employed to model hardware resources of the processor and instructions of program traces. They are exploited to investigate the probability of input errors to alter both the correct behavior and the output of the program. Experimental results show that Bayesian networks prove to be a promising model, allowing to get accurate and fast reliability estimations w.r.t. fault injection/simulation approaches.

Fault tolerant (or dependable) computing has always been an exciting research area in the intersection of computer science and engineering and electrical and electronics engineering. During the last two decades the applicability of the methods and tools that the fault tolerance research community produces has expanded to virtually all application domains. The type of fault tolerance methods employed in a computing system depend on: (a) the faults expected to affect the system, (b) the importance of errors in the system operation, (c) the design, cost and power budgets that can allocated to fault tolerance and reliable operation. New solutions and tools in fault tolerant computing are emerging to deal with the very broad spectrum of values that all (a), (b) and (c) can take in today's computing landscape.

Analyzing the impact of software execution on the reliability of a complex digital system is an increasing challenging task. Current approaches mainly rely on time consuming fault injections experiments that prevent their usage in the early stage of the design process, when fast estimations are required in order to take design decisions. To cope with these limitations, this paper proposes a statistical reliability analysis model based on Bayesian Networks. The proposed approach is able to estimate system reliability considering both the hardware and the software layer of a system, in presence of hardware transient and permanent faults. In fact, when digital system reliability is under analysis, hardware resources of the processor and instructions of program traces are employed to build a Bayesian Network. Finally, the probability of input errors to alter both the correct behavior of the system and the output of the program is computed. According to experimental results presented in this paper, it can be stated that Bayesian Network model is able to provide accurate reliability estimations in a very short period of time. As a consequence it can be a valid alternative to fault injection, especially in the early stage of the design.

Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.). However, the same path that is leading technologies toward these remarkable achievements is also making electronic devices increasingly unreliable, posing a threat to our society that is depending on the ICT in every aspect of human activities. Reliability of electronic systems is therefore a key challenge for the whole ICT technology and must be guaranteed without penalizing or slowing down the characteristics of the final products. CLERECO EU FP7 (GA No. 611404) research project addresses early accurate reliability evaluation and efficient exploitation of reliability at different design phases, since these aspects are two of the most important and challenging tasks toward this goal.

Evaluation of computing systems reliability must be accurate enough to provide hints for the required fault protection mechanisms that will guarantee correctness of operation at acceptance costs. To be useful, reliability evaluation must be performed early enough in the design cycle when, however, the available details of the system are largely unknown. This inherent contradiction in terms: early vs. accurate, requires a cross-layer approach for reliability evaluation. Different layers of abstraction contribute differently in the overall system reliability; if this contribution can be assessed independently, the reliability of the system can be evaluated at the early stages of the design. We review the state-of-the-art in the area and discuss corresponding challenges .

Forthcoming technologies hold the promise of a significant increase in integration density, performance and functionality. However, a dramatic change in microprocessor's reliability is also expected. Developing mechanisms for early and accurate reliability estimation will save significant design effort, resources and consequently will positively impact product's time-to-market (TTM). In this paper, we propose a versatile architecture-level fault injection framework, built on top of a state-of-the-art x86 microprocessor simulator, for thorough and fast characterization of a wide range of hardware components with respect to various fault models.

In the era of terascale integration, the “reliability wall” and the “power wall” arise as barriers imposing significant challenges to the microprocessor industry. Nowadays, on-line testing is essential for modern microprocessors to detect latent defects that either escaped manufacturing testing or appear during system operation. Moreover, many-core scaling is now facing the “power wall”. More cores can now be placed on a chip than can be concurrently operating due to energy/power limitations. Software-Based Self-Test (SBST) is a flexible and low-cost solution for on-line March test application and defect detection in small memories, such as L1 caches, that lack Memory Built-In Self-Test (MBIST) hardware. In this paper, a power-aware optimization of the SBST methodology introduced in [10] is presented targeting Ll caches by analyzing the unique characteristics of March SBST routines and possible power optimizations without sacrificing March test quality. Experimental results using an architectural-level-power evaluation framework based on GEM5 and McPAT show that the exploitation of Direct Cache Access (DCA) instructions introduced in [10] along with the application of compiler-based power optimizations can achieve significant power savings up to 82.27% and energy savings up to 84,89% for the UltraSPARC Tl processor core. To the best of our knowledge, this is the first paper that addresses power-aware SBST for L1 caches in microprocessors.

In-field testing of SoC devices is increasingly important to face the dependability requirements of several application domains. Different solutions can be devised and adopted. We summarize the main solutions currently adopted by industry, identify the most critical open issues, and discuss important future trends.

Forthcoming many-core processors are expected to be highly unreliable due to their high design complexity and aggressive manufacturing technology scaling. Online functional testing is an attractive low-cost error detection solution. A functional error detection scheme for many-core architectures can easily employ existing techniques from single-core microprocessors and exploit the available massive parallelism to reduce the total test execution time. However, the straightforward execution of test programs on such parallel architectures does not achieve the maximum theoretical speedup due to severe congestion on common hardware resources, especially the shared memory and the interconnection network. In this paper, we first identify the memory hierarchy parameters of many-core architectures that slow down the execution of parallel test programs. Then, we study typical test programs to identify which of their parts can be parallelized to improve performance. Finally, we propose a test program parallelization methodology for many-core architectures to accelerate online detection of permanent faults. We evaluate the proposed methodology on a popular many-core architecture, Intel's Single-chip Cloud Computer (SCC) showing an up to 47.6X speedup compared to a serial test program execution approach.

Nowadays, on-line testing is essential for modern microprocessors to detect latent defects that either escape manufacturing testing or appear during system operation. Small memories, such as L1 caches and translation lookaside buffers (TLBs) are not usually equipped with memory built-in self-test (MBIST) hardware. Software-based self-test (SBST) is a flexible and low-cost solution for on-line March test application and error detection in such small memories. Although, L1 caches and TLBs are small components, their reliable operation is crucial for the system performance due to the large penalties caused when L1 cache or TLB misses occur. In this paper, an SBST program development methodology is proposed for on-line testing of small cache memories in microprocessors. To overcome testability challenges that are due to the “hidden” or implicit operation of such memories, the proposed SBST methodology exploits: 1) existing special purpose instructions that modern instruction set architectures implement to access these cache arrays for debug-diagnostic (DD) purposes, termed hereafter direct cache access instructions and 2) performance monitoring and trap handling mechanisms. Besides, the proposed SBST methodology combines features that are crucial for on-line testing: a) compact test validation; b) simplified coding style; c) low invasiveness of the test program; and d) small memory footprint. The methodology is comprehensively demonstrated on the instruction and data L1 cache arrays and the instruction and data TLB arrays of OpenSPARC T1. Experimental results show that the exploitation of such DD instructions has a significant improvement of test time (up to 86% for instruction L1 cache, up to 87% for the data L1 cache, up to 37% for D-TLB, and up to 91% for I-TLB) when compared to SBST solutions that do not utilize these types of instructions.

Forthcoming technology nodes are posing major challenges on the manufacturing of reliable (real-time) systems: process variations, accelerated degradation aging, as well as external and internal noise are key examples. This paper focuses on real-time systems reliability and analyzes the state-of-the-art and the emerging reliability bottlenecks from three different perspectives: technology, circuit/IP and full system.

A growing portion of the silicon area of modern high-performance microprocessors is dedicated to components that increase performance but do not determine functional correctness. Permanent hardware faults in these components can lead to performance fluctuation (not necessarily degradation) and do not produce functional errors. Although this fact has been identified previously, extensive research has not yet been conducted to accurately classify and quantify permanent faults in these components over a set of CPU benchmarks or measure the magnitude of the performance impact. Depending on the results of such studies, performance-related components of microprocessors can be disabled in fine or coarse granularities, salvaging microprocessor functionality at different performance levels. This paper analyzes the impact of permanent faults in the arrays and control logic of key microprocessor performance components such as the branch predictor, branch target buffer, return address stack, and data and instruction prefetchers. We apply a statistically safe fault injection campaign for single faults in performance components on a modified version of the cycle-accurate x86 architectural simulator PTLsim running the SPEC CPU2006 suite. Our evaluation reveals significant differences in the effect of faults and their performance impacts across the components as well as within each component (different fields). We classify faults for all components and analyze their IPC impact in the arrays and control logic. Our analysis shows that a very large fraction (44% to 96%) of permanent faults in these components leads only to performance fluctuation. Observation confirms the intuition that there are no functionality errors; however, many cases of a single fault in a performance component can significantly degrade microprocessor performance (2-20%average IPC reduction for SPEC CPU2006).

Large silicon parts of modern microprocessors are dedicated to components that increase performance but don't determine functional correctness. Permanent hardware faults in such components lead to performance fluctuation (not necessarily degradation) but do not produce functional errors. This fact has been identified previously but neither an accurate classification of the behavior of permanent faults in these components over a set of CPU benchmarks nor detailed measurements of the magnitude of their performance impact has been reported. Depending on such measurements the performance-related components of microprocessors can be disabled in fine or coarse granularities, salvaging the microprocessor functionality although at different performance levels. In this paper, we describe a comprehensive framework for the analysis of the impact of permanent faults in the arrays and the control logic of key performance components. We apply a statistically safe, fault injection campaign to the performance components on a modified version of the cycle accurate x86-based architectural simulator PTLsim running the SPEC2006 benchmarks suite. Our evaluation reveals the differences in the effect of faults and their performance impact across the components as well as within each component. We summarize the fault effect classification and further analyze the performance impact (IPC) of faults in their arrays and control parts.

Multicore architectures are employed in the majority of computing domains (general-purpose microprocessors as well as specialized high-performance architectures such as network processors). Online error detection in such chips can employ effective techniques from single core microprocessors, however, effective test scheduling should be employed to minimize the overall chip test execution time which can significantly increase due to congestion on common hardware resources used by the cores. In this paper, we analyze the most important aspects of online error detection and scheduling in multiprocessor chips and evaluate test execution time in several different configurations of Intel's SCC architecture.

Massively parallel many-core Graphics Processing Unit (GPU) architectures offer significant performance speedup in workloads with thread-level parallelism compared to contemporary multicore CPUs. For this reason, general-purpose computing using GPUs (GPGPU) is a rapidly expanding research direction in different contexts. Unlike graphics processing, GPGPU computing requires reliable operation in the presence of hardware faults whose occurrence probabilities in current and forthcoming advanced manufacturing technologies will be significant. In this paper, we focus on the aspect of tolerance of GPUs to permanent faults in their most critical storage elements: register files. By performing a comprehensive fault injection campaign on a cycle-accurate GPGPU architectural simulator, we first evaluate and classify the behavior of NVIDIA GPU CUDA kernels in the presence of permanent faults in registers. Moreover, we analyze the performance tolerance of GPUs when they operate in degraded mode (less hardware resources, less thread-level parallelism) due to the presence of multiple permanent faults in the registers of their streaming multiprocessors. Our findings confirm the intuitively expected tolerance of these architectures to faults and also quantify it in different configurations and modes.

The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of "noise" in this phase is that large numbers of random test programs fail due to the same or similar design bugs. This redundant behavior adds long delays in the debug flow since each failing random program must be separately examined, although it does not usually bring new debug information. The development of effective techniques that detect dominant modes of failure among random programs and triage them into common categories eliminate redundant debug sessions and significantly boost silicon debug.

SRAM-based FPGAs provide an attractive solution for building high-performance embedded computing systems. Fault tolerant mechanisms are usually implemented in FPGA-based critical systems to improve their vulnerability to transient faults. Most fault tolerant approaches proposed so far in the literature for FPGA systems utilize checkpointing and scrubbing techniques for the fault recovery and repair operations, respectively, and rely on redundancy-based fault detection solutions. In this paper, we study the feasibility of building a low-cost fault-tolerant approach for FPGA-based realtime systems that combines checkpointing and scrubbing, the latter for both fault detection and repair. We calculate the checkpoint frequencies that guarantee the execution of the tasks within their deadlines in the presence of transient faults, taking into consideration the scrubbing time of the FPGA processor. Furthermore, we propose a selective scrubbing approach to reduce the scrubbing time and make feasible the fault tolerant execution of tasks with tight deadlines. We demonstrate the proposed approach in a Leon-3-based SoC in a Virtex-5 FPGA.

The flexibility that allows the application of different March tests is a critical requirement for on-line testing of memory arrays. In a previous study, we have introduced a low-cost software-based self test (SBST) program development methodology for on-line periodic testing of L1 caches that utilizes direct cache access (DCA) instructions and exploits the native monitoring hardware available in modern architectures. In this brief, we discuss a multithreaded optimization of this SBST methodology that exploits the thread level parallelism of multithreaded multicore architectures in order to speed up March test execution by elaborating the low level multiple sub-bank cache organization. The effectiveness of the methodology and its multithreaded optimization is demonstrated on the L1 caches of OpenSPARC T1 processor. Our results showed a speedup of more than 1.7 when the multithreaded optimization is applied and an acceptable performance overhead (less than 11%), even in intensive periodic test scenarios.

For small memory arrays that usually lack Memory Built-In Self-Test (MBIST), such as Translation Lookaside Buffer (TLB) arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for on-line testing of data TLB (D-TLB), both for data (SRAM) and tag (CAM) memory arrays. The SBST methodology exploits existing special purpose instructions that modern ISAs implement to access the TLBs for debug-diagnostic purposes, termed hereafter Direct TLB Access (DTA) instructions, as well as, the trap handler mechanism.

Wireless Sensor Network (WSN) nodes are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly increased, while silicon aging effects are also exacerbated. Thus, online and in-field testing is necessary to guarantee correctness of operation. At the same time, online testing of processors integrated in WSN nodes has the requirement of minimum energy consumption, because these devices operate on battery, cannot be connected to any external power supply, and the battery duration determines the lifetime of the system. Software-Based Self-Test (SBST) has emerged as an effective strategy for online testing of processors integrated in nonsafety critical applications. However, the notion of dependability includes not only reliability but also availability. Thus, in order to encase both aspects we present a methodology for the optimization of SBST routines from the energy perspective. The refined methodology presented in this paper is able to be effectively applied in the case that the SBST routines are not initially available and need to be downloaded to the WSN nodes, as well as the case that the SBST routines are available in a flash memory. The methodology is extended to maximize the energy gains for WSN architectures offering clock gating or Dynamic Frequency Scaling features. Simulation results show that energy savings at processor level are up to 36.5 percent, which depending on the characteristics of the WSN system, can translate in several weeks of increased lifetime, especially if the routines need to be downloaded to the WSN node.

In modern processes, conventional defect density and variability related yield losses are a major concern for the aggressive memory designs in integrated circuits. Synergistic action for memory repair at the circuit and architectural level is essential to maintain the yields and profitability of past technology nodes. In this paper, we propose a scalable memory repair architecture that utilizes a set of direct-mapped cache banks to replace faulty words. Statistical and mathematical probability analysis shows that the proposed scheme achieves high repairability levels with low area and static power dissipation overheads, the latter being a dominant issue in nanometer technologies. It is therefore a suitable solution along with other mature memory repair techniques, to enhance the overall repairability features and guarantee the correct and reliable operation of embedded memories in nanometer technologies.

Weighted pseudorandom built-in self test (BIST) schemes have been utilized in order to drive down the number of vectors to achieve complete fault coverage in BIST applications. Weighted sets comprising three weights, namely 0, 1, and 0.5 have been successfully utilized so far for test pattern generation, since they result in both low testing time and low consumed power. In this paper an accumulator-based 3-weight test pattern generation scheme is presented; the proposed scheme generates set of patterns with weights 0, 0.5, and 1. Since accumulators are commonly found in current VLSI chips, this scheme can be efficiently utilized to drive down the hardware of BIST pattern generation, as well. Comparisons with previously presented schemes indicate that the proposed scheme compares favorably with respect to the required hardware.

The huge investment in the design and production of multicore processors may be put at risk because the emerging highly miniaturized but unreliable fabrication technologies will impose significant barriers to the life-long reliable operation of future chips. Extremely complex, massively parallel, multi-core processor chips fabricated in these technologies will become more vulnerable to: (a) environmental disturbances that produce transient (or soft) errors, (b) latent manufacturing defects as well as aging/wearout phenomena that produce permanent (or hard) errors, and (c) verification inefficiencies that allow important design bugs to escape in the system. In an effort to cope with these reliability threats, several research teams have recently proposed multicore processor architectures that provide low-cost dependability guarantees against hardware errors and design bugs. This paper focuses on dependable multicore processor architectures that integrate solutions for online error detection, diagnosis, recovery, and repair during field operation. It discusses taxonomy of representative approaches and presents a qualitative comparison based on: hardware cost, performance overhead, types of faults detected, and detection latency. It also describes in more detail three recently proposed effective architectural approaches: a software-anomaly detection technique (SWAT), a dynamic verification technique (Argus), and a core salvaging methodology.

Performance demand of Critical Real-Time Embedded (CRTE) systems implementing safety-related system features grows at an exponential rate. Only modern semiconductor technologies can satisfy CRTE systems performance needs efficiently. However, those technologies lead to high failure rates, thus lowering survivability of chips to unacceptable levels for CRTE systems. This paper presents SESACS architecture (Surviving Errors in SAfety-Critical Systems), a paradigm shift in the design of CRTE systems. SESACS is a new system design methodology consisting of three main components: (i) a multicore hardware/firmware platform capable of detecting and diagnosing hardware faults of any type with minimal impact on the worst-case execution time (WCET), recovering quickly from errors, and properly reconfiguring the system so that the resulting system exhibits a predictable and analyzable degradation in WCET; (ii) a set of analysis methods and tools to prove the timing correctness of the reconfigured system; and (iii) a white-box methodology and tools to prove the functional safety of the system and compliance with industry standards. This new design paradigm will deliver huge benefits to the embedded systems industry for several decades by enabling the use of more cost-effective multicore hardware platforms built on top of modern semiconductor technologies, thereby enabling higher performance, and reducing weight and power dissipation. This new paradigm will further extend the life of embedded systems, therefore, reducing warranty and early replacement costs.

Nowadays, on-line testing is essential for modern high-density microprocessors to detect either latent hardware defects or new defects appearing during lifetime both in logic and memory modules. For cache arrays, the flexibility to apply online different March tests is a critical requirement. For small memory arrays that may lack programmable Memory Built-In Self-Test (MBIST) circuitry, such as L1 cache arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for online periodic testing of L1 data and instruction cache, both for tag and data arrays. The proposed SBST methodology utilizes existing special purpose instructions that modern Instruction Set Architectures (ISAs) implement to access caches for debug-diagnostic and performance purposes, termed hereafter Direct Cache Access (DCA) instructions, as well as, performance monitoring mechanisms to overcome testability challenges. The methodology has been applied to 2 processor benchmarks, OpenRISC and LEON3 to demonstrate its high adaptability, and experimental comparison results against previous contributions show that the utilization of DCA instructions significantly improves test code size (83%) and test duration (72%) when applied to the same benchmark (LEON3).

Microprocessor design validation is a time consuming and costly task that tends to be a bottleneck in the release of new architectures. The validation step that detects the vast majority of design bugs is the one that stresses the silicon prototypes by applying huge numbers of random tests. Despite its bug detection capability, this step is constrained by extreme computing needs for random tests simulation to extract the bug-free memory image for comparison with the actual silicon image.

COMPUTER architecture is a wide active research field that spans all aspects of computer systems design. Dependability the trustworthiness of a computing system which allows reliance to be justifiably placed on the service it delivers has always been a key aspect of computer architecture and has been extensively investigated since the first days of computing. Traditionally, dependable computer architectures are utilized in high-end computing systems or computing systems for critical applications, where continuous, uninterrupted operation is among the most important requirements and systems are characterized by high reliability, availability, and maintainability (wellknown measures to quantify dependability). The time has now come for the wealth of concepts and methodologies in the field of dependable (also known as fault-tolerant) computer architecture that have been proposed during the last several decades, to be adopted and extended in mainstream, general-purpose computing systems. Dependable operation of computing systems is a mandatory requirement in virtually all application fields (at lower or higher costs), due to the increasing reliance of everyday human activities on computers or microprocessor-based systems in general. Unfortunately, this ubiquitous computing revolution comes in hand with hard-tosolve technological issues that are closely related to dependable operation of a computing system. Integrated circuits are implemented today in miniaturized and inherently unreliable technologies that render circuits more vulnerable to both temporary disturbances leading to transient (or soft) errors and to permanent (or hard) errors. Soft errors in silicon-based circuits are caused by alpha particles from integrated circuit package decay or by cosmic rays that create high energy neutrons and protons. Hard errors, on the other side, appear either because of manufacturing defects that escape high-volume production manufacturing testing or because of material aging and wearout mechanisms during the system’s life cycle that are exacerbated by the high clock frequencies of modern circuits. Computing systems are getting constantly more complex (in particular with the recent turn toward multicore processors and high performance memory systems) while on the same time strict time-to-market constraints demand for extremely short design, verification, and validation intervals. The net outcome of all the previous factors is that dependable operation of computing systems in the field should be a first level design consideration in all application domains, obviously at different cost points. This special section of IEEE Transactions on Computers focuses on architectural techniques that enhance dependability of different components of a computing system. A total number of 27 high-quality manuscripts were submitted to the special section from academic and industrial research groups worldwide, and a large set of more than 140 reviews from a strong group of expert reviewers was required to make final decisions. This special section published in the current issue of IEEE Transactions on Computers includes seven of the papers; roughly one fourth of the submitted papers on this topic. The seven papers of the special section on Dependable Computer Architecture cover a wide spectrum of subsystems of mainstream architectures: processors (in particular CMP), cache memories, flash, and disk storage, but also a paper on probabilistic (stochastic) architectures is included. Methodologies are proposed for effective handling of both hard and soft errors and the papers of the special section comprehensively discuss all major tradeoffs between dependability and other design aspects such as performance, cost, yield, energy/power. The first paper entitled “StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs”, by Shantanu Gupta, Shuguang Feng, Amin Ansari, and Scott Mahlke from the University of Michigan, Ann Arbor, opens the special section dealing with tolerance of progressively higher defect densities due to aging in massively parallel chip multiprocessors (CMPs). The authors present StageNet, a reconfigurable CMP architecture that is primarily designed to provide fault tolerance and extend the lifetime of the system which gracefully degrades as the number of permanent faults increases. The subsequent three papers focus on different aspects of cache memories with respect to dependability. The second paper of the special section entitled “Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache”, by Somnath Paul, Fang Cai, Xinmiao Zhang, and Swarup Bhunia, from Case Western Reserve University, discusses a non-uniform, variable ECC allocation scheme to effectively tolerate multiple bit errors in cache memories. The method utilizes post-fabrication characterization information to provide different ECC allocation depending on the relative vulnerability of cache memory blocks. IEEE TRANSACTIONS ON COMPUTERS, VOL. 60, NO. 1, JANUARY 2011 3

We study chip self-organization and fault tolerance at the architectural level to improve dependable continuous operation of multicore arrays in massively defective nanotechnologies. Architectural self-organization results from the conjunction of self-diagnosis and self-disconnection mechanisms (to identify and isolate most permanently faulty or inaccessible cores and routers), plus self-discovery of routes to maintain the communication in the array. In the methodology presented in this work, chip self-diagnosis is performed in three steps, following an ascending order of complexity: interconnects are tested first, then routers through mutual test, and cores in the last step. The mutual testing of routers is especially important as faulty routers are disconnected by good ones with no assumption on the behavior of defective elements. Moreover, the disconnection of faulty routers is not physical (“hard”) but logical (“soft”) in that a good router simply stops communicating with any adjacent router diagnosed as defective. There is no physical reconfiguration in the chip and no need for spare elements. Ultimately, the multicore array may be viewed as a black box, which incorporates protection mechanisms and self-organizes, while the external control reduces to a simple chip validation test which, in the simplest cases, reduces to counting the number of valid and accessible cores.

Wireless Sensor Network (WSN) applications often need to be deployed in harsh environments, where the possibility of faults due to environmental hazards is significantly increased, while silicon aging and wearout effects are also exacerbated. For such applications, periodic on-line testing of the WSN nodes is an important step towards correctness of operation. However, on-line testing of processors integrated in WSN nodes has to address the additional challenge of minimum energy consumption, because these devices operate on battery, which usually cannot be replaced and in the absence of catastrophic failures determines the lifetime of the system. In this paper initially we derive analytically the optimal way for executing on-line periodic test with adjustable period, taking into account the degrading behavior of the system due to silicon aging effects but also the limited energy budget of WSN applications. The test is applied in the form of Software-Based Self-Test (SBST) routines, thus we proceed to the power optimized development of SBST routines targeting the transition delay fault model that is well suited for detecting timing violations due to silicon aging. Simulation results show that energy savings for the final SBST routine at processor level are up to 35.4% and the impact of test in the battery life of the system is negligible.

Software-Based Self-Test (SBST) has emerged as an effective method for on-line testing of processors integrated in non safety-critical systems. However, especially for multi-core processors, the notion of dependability encompasses not only high quality on-line tests with minimum performance overhead but also methods for preventing the generation of excessive power and heat that exacerbate silicon aging mechanisms and can cause long term reliability problems. In this paper, we initially extend the capabilities of a multiprocessor simulator in order to evaluate the overhead in the execution of the useful application load in terms of both performance and energy consumption. We utilize the derived power evaluation framework to assess the overhead of SBST implemented as a test thread in a multiprocessor environment. A range of typical processor configurations is considered. The application load consists of some representative SPEC benchmarks, and various scenarios for the execution of the test thread are studied (sporadic or continuous execution). Finally, we apply in a multiprocessor context an energy optimization methodology that was originally proposed to increase battery life for battery-powered devices. The methodology reduces significantly the energy and performance overhead without affecting the test coverage of the SBST routines.

Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in-system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March test application and thus a viable supplement to hardware approaches. In this paper, a generic SBST program development methodology is proposed for periodic in-system (on-line) testing of L1 data and instruction cache memory tag arrays (both for direct mapped and set associative organization) based on contemporary March test algorithms. The proposed SBST methodology utilizes existing special performance instructions and performance monitoring mechanisms of modern processors to overcome cache tag testability challenges. Experimental results on OpenRISC 1200 processor core demonstrate that high test quality of contemporary March test algorithms is preserved while low-cost in-system testing in terms of test duration and test code size is achieved.

Instruction-based or software-based self-testing (SBST) is a scalable functional testing paradigm that has gained increasing acceptance in testing of single-threaded uniprocessors. Recent computer architecture trends towards chip multiprocessing and multithreading have raised new challenges in the test process. In this paper, we present a novel self-test optimization strategy for multithreaded, multicore microprocessor architectures and apply it to both manufacturing testing (execution from on-chip cache memory) and post-silicon validation (execution from main memory) setups. The proposed self-test program execution optimization aims to: (a) take maximum advantage of the available execution parallelism provided by multiple threads and multiple cores, (b) preserve the high fault coverage that single-thread execution provides for the processor components, and (c) enhance the fault coverage of the thread-specific control logic of the multithreaded multiprocessor. The proposed multithreaded (MT) SBST methodology generates an efficient multithreaded version of the test program and schedules the resulting test threads into the hardware threads of the processor to reduce the overall test execution time and on the same time to increase the overall fault coverage. We demonstrate our methodology in the OpenSPARC T1 processor model which integrates eight CPU cores, each one supporting four hardware threads. MT-SBST methodology and scheduling algorithm significantly speeds up self-test time at both the core level (3.6 times) and the processor level (6.0 times) against single-threaded execution, while at the same time it improves the overall fault coverage. Compared with straightforward multithreaded execution, it reduces the self-test time at both the core level and the processor level by 33% and 20%, respectively. Overall, MT-SBST reaches more than 91% stuck-at fault coverage for the functional units and 88% for the entire chip multiprocessor, a total of more than 1.5M logic gates.

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In (n,k)-adjacent bit pseudo-exhaustive test sets, all 2kbinary combinations appear to all adjacentk-bit groups of inputs. With recursive pseudoexhaustive generation, all (n,k)-adjacent bit pseudoexhaustive tests are generated fork¿nand more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern (n,k)-adjacent bit pseudoexhaustive tests for allk¿n. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.

Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional self-testing is performed by test programs that the processor executes at-speed from on-chip memory. Multiprocessors and multithreaded architectures are constantly becoming the typical general-purpose computing paradigm, and thus the various existing uniprocessor functional self-testing schemes must be adopted and adjusted to meet the testing requirements of complex multiprocessors. A major challenge in porting a functional self-testing approach from the uniprocessor to the multiprocessor case is to take advantage of the inherent execution parallelism offered by the multiple cores and the multiple threads in order to reduce test execution time. In this paper, we study the application of functional self-testing to chip multithreaded (CMT) processors. We propose a method that exploits thread-level parallelism (TLP) to speed up the execution of self-test routines in every physical core of a multiprocessor chip. The proposed method effectively splits the self-test routines into shorter ones, assigns the new routines to the hardware threads of the core and schedules their execution in order to minimize the core idle intervals due to cache misses or long latency operations and maximize the utilization of core computing resources. We demonstrate our method in the open-source CMT multiprocessor model, Sunpsilas OpenSPARC T1, which contains eight CPU cores, each one supporting four hardware threads. Our experimental results show a self-test execution speedup of more than three times compared to the single thread execution.

As we move deeper in the nanotechnology era, computer architecture is solicited to manipulate tremendous numbers of devices per chip with high defect densities. These trends provide new computing opportunities but efficiently exploiting them will require a shift towards novel, highly parallel architectures. Fault tolerant mechanisms will have to be integrated to the design to deal with the low yield of future nanofabrication processes. In this paper we consider multi processor grid (MPG) architectures that assure scalability beyond hundreds of cores per chip. We study self-diagnosis and self-configuration methods at the architectural level and propose an enhanced self-configuration methodology that enables usage of a maximum percentage of available fault-free cores in MPGs with high defect densities. We show that our approach achieves usability of all fault-free cores for the case of fault-free routers whereas previous work was efficient for defect densities of up to 20-25% of defective cores. We also address the case of faulty routers, achieving usability of almost all fault-free nodes (fault-free cores having a fault-free router) for very high defect densities both in the cores and in the routers.

Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent Test Latency of an input vector monitoring scheme is the time required for the concurrent test to complete. Input Vector Monitoring Concurrent BIST schemes that have been proposed to date, are based mainly on test sets containing binary (1 or 0) values. Test sets extracted by modern CAD tools, largely contain don't care (dasiaXpsila) values. In this work a novel input vector monitoring concurrent BIST scheme is presented, based on a test set containing dasiaXpsila values. The proposed scheme compares favourably with respect to the hardware overhead - concurrent test latency trade off with previously proposed techniques.

Software-based or instruction-based self-testing has recently emerged as an effective alternative for the manufacturing and online testing of microprocessors, and is progressively adopted by major microprocessor manufacturers mainly as a supplement to other mature and well-established testing approaches to reach higher test quality. Thus far, software-based self-test approaches presented in the literature have focused almost exclusively on uniprocessors. With the continuing prevalence of multiprocessors, the focus of such research approaches moves from the uniprocessor to the multiprocessor case. In this paper, we study the application of software-based self-testing on symmetric shared-memory multiprocessors (SMP) considering the most common interconnection architectures, shared bus and crossbar switch. We focus on the impact of the shared-memory system architecture, the cache coherence mechanisms, and the interconnection architecture on the execution time of self-test programs running on each separate core and exploit the SMP's parallelism during testing to reduce the test execution time. We propose a generic methodology that allocates the test programs and test responses into the shared on-chip memory and schedules the test routines among the cores aiming at the reduction of the total test application time, and thus, test cost, for the SMP, by increasing the execution parallelism and reducing both bus contentions and data cache invalidations. We demonstrate the proposed solutions with detailed experiments on several two-core, four-core, and eight-core SMP benchmarks based on a popular RISC benchmark processor using both the shared bus and the crossbar switch interconnection architectures.

Online periodic self-testing is a cost-effective technique to ensure correct operation of microprocessor-based systems in the field and improve their dependability in the presence of failures caused by components aging/wearout. Effective online self-test tasks in embedded systems should have limited resource requirements: memory, execution time, and power consumption, while at the same time, they should guarantee the highest possible self-test quality levels. These requirements are not always easy to satisfy in real-time embedded systems with hard task deadlines. In this paper, we investigate the maximization of the effective self-test utilization and present solutions for the scheduling of online self-test tasks in hard real-time systems. The primary goal is to guarantee high self-test quality without affecting the deadline requirements of normal hard real-time tasks. We show that with appropriate selection of the periodicity of the self-test tasks, these goals can be met.

Online periodic testing of microprocessors is a valuable means to increase the reliability of a low-cost system, when neither hardware nor time redundant protection schemes can be applied. This is particularly valid for floating-point (FP) units, which are becoming more common in embedded systems and are usually protected from operational faults through costly hardware redundant approaches. In this paper, we present scalable instruction-based self-test program development for both single and double precision FP units considering different instruction sets (MIPS, PowerPC, and Alpha), different microprocessor architectures (32/64-bit architectures) and different memory configurations. Moreover, we introduce bit-level manipulation instruction sequences that are essential for the development of FP unit's self-test programs. We developed self-test programs for single and double precision FP units on 32-bit and 64-bit microprocessor architectures and evaluated them with respect to the requirements of low-cost online periodic self-testing: fault coverage, memory footprint, execution time, and power consumption, assuming different memory hierarchy configurations. Our comprehensive experimental evaluations reveal that the instruction set architecture plays a significant role in the development of self-test programs. Additionally, we suggest the most suitable self-test program development approach when memory footprint or low power consumption is of paramount importance.

Functional, instruction-based self-testing of microprocessors has emerged as an effective alternative or supplement to other testing approaches, and is progressively adopted by major microprocessor manufacturers. In this paper, we study, for first time, the applicability of functional self-testing on bus-based symmetric multiprocessors (SMP) and the exploitation of SMPs parallelism during testing. We focus on the impact of the memory system architecture and the cache coherency mechanisms on the execution of self-test programs on the processor cores. We propose a generic self-test routines scheduling algorithm aiming at the reduction of the total test application time for the SMP by reducing both bus contention and data cache coherency invalidation. We demonstrate the proposed solutions with detailed experiments in two-core and four-core SMP benchmarks based on a RISC processor core.

Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical applications. Among the various systems that fall in the previous category, wireless sensor networks (WSN) are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly increased, thus on-line and in-field testing is necessary to guarantee the accuracy of the sensed values. At the same time, on-line testing of processors integrated in WSN has the extra requirement of minimum energy consumption, because these devices are operating on battery, cannot be connected to any external power supply, and the battery duration determines the lifetime of the system. In this paper we present a methodology for the optimization of SBST routines from the energy perspective. Techniques utilized for achieving energy reduction include energy aware loop synthesis, loop transformations, instruction substitution and register renaming. Simulation results show that the energy savings at processor level are up to 35.6%.

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach.

Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the most popular applications falling in this category are the various mobile devices. However, in-field testing of processors integrated in mobile devices has the extra requirement of minimum energy consumption, since these devices are operating on battery. In this paper initially we present the parameters contributing to energy consumption in order to set the scope of the problem and make a qualitative analysis about the efficiency of the SBST routines from a low energy perspective. Then we propose a power evaluation framework based on a combination of tools from the testing and computer architecture technical areas. Utilizing this framework we evaluate for the first time the most effective structural SBST strategies in terms of energy consumption for three representative processor configurations, showing the validity of our analysis. Finally, the SBST strategies are combined and an appropriate strategy for each processor component is selected, in order to minimize overall energy consumption during on-line testing up to an order of magnitude between the best and worst case combination of test routines.

Functional Software-Based Self-Testing (SBST) of microprocessors and processor-based testing of Systems-on- Chip (SoCs) have recently attracted the attention of test technology research community because they provide an effective alternative to other traditional testing and self- testing approaches. SBST allows at-speed functional testing of SoC cores with virtually no circuit overhead and limited dependence on external testers. Despite the importance of peripheral control cores in SoCs (in terms of functionality and size), the applicability and limits of SBST on them have not been comprehensively studied. In this paper, we study the effectiveness of SBST on a broad class of communication peripherals. A systematic application of SBST on two popular peripheral cores (UART and Ethernet) demonstrates the effectiveness of SBST on SoCs with such cores.

Speculative execution of instructions boosts performance in modern microprocessors. Control and data flow dependencies are overcome through speculation mechanisms, such as branch prediction or data value prediction. Because of their inherent self-correcting nature, the presence of defects in speculative execution units does not affect their functionality (and escapes traditional functional testing approaches) but impose severe performance degradation. In this paper, we investigate the effects of performance faults in speculative execution units and propose a generic, software-based test methodology, which utilizes available processor resources: hardware performance monitors and processor exceptions, to detect these faults in a systematic way. We demonstrate the methodology on a publicly available fully pipelined RISC processor that has been enhanced with the most common speculative execution unit, the branch prediction unit. Two popular schemes of predictors built around a Branch Target Buffer have been studied and experimental results show significant improvements on both cases fault coverage of the branch prediction units increased from 80% to 97%. Detailed experiments for the application of a functional self-testing methodology on a complete RISC processor incorporating both a full pipeline structure and a branch prediction unit have not been previously given in the literature.

Software-based self-testing (SBST) of microprocessors and processor-based testing of systems-on-chip (SoCs) recently captured intense test technology research efforts because they provide an effective alternative or supplement to other classic testing and self-testing approaches. Despite the importance of peripheral cores in SoCs (in terms of functionality and size), the applicability and limits of SBST on them have not been comprehensively studied. In this paper, we study the effectiveness of SBST on a broad class of communication peripheral cores in SoCs. A systematic application of SBST on two popular peripherals (universal asynchronous receiver transmitter and Ethernet) demonstrates the effectiveness of SBST on SoCs with such cores.

The five papers in this special section focus on autonomous silicon validation and testing of microprocessors and microprocessor-based systems. The papers cover several important aspects of the technical area: from first silicon validation and debug to manufacturing and production testing, including both software-based and hardware-based techniques and design-for-test methods that range from pure functional instruction-based to structural scan-based tests. The scope of the papers extends from embedded uniprocessors to multicore microprocessors.

Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC’s interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs. We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15% (12 % on average) for the entire processor, and fault coverage improvements of 22 % for the pipeline logic, compared to a conventional SBST approach.

Today's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operation. Since software-based self-test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical low-cost embedded system applications, optimal test period specification is becoming increasingly challenging. In this paper we first introduce a reliability analysis for optimal periodic testing of intermittent faults that minimizes the test cost incurred based on a two-state Markov model for the probabilistic modeling of intermittent faults. Then, we present for the first time an enhanced SBST strategy for on-line testing of complex pipelined embedded processors. Finally, we demonstrate the effectiveness of the proposed optimal periodic SBST strategy by applying it to a fully-pipelined RISC embedded processor and providing experimental results

In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We propose a method for significantly reducing the fault list by removing the faults on unused LUT bit positions. We also target the design flip-flops found in the configurable logic blocks (CLBs) inside the FPGA. Run-time reconfigurability of Virtex devices using JBits is exploited to provide the means not only for fault injection but fault detection as well. First, we consider five possible application scenarios for evaluating different self-test schemes. Then, we apply the least favorite and most time consuming of these scenarios on two 32times32 multiplier designs, demonstrating that transferring the simulation processing workload to FPGA hardware can allow for acceleration of simulation time of more than two orders of magnitude

High-speed datapaths in microprocessors and embedded processors contain complex floating-point (FP) arithmetic units which have a critical role in the processor's performance. Although the FP units' complex structure consists of classic integer arithmetic components, the embedded components encounter serious testability problems due to their limited accessibility from the FP unit ports and testability loss due to FP unit inherent operations, such as rounding and normalization. In this paper, we analyze the testability problems and present scalable test generation for FP units using as a demonstration vehicle the popular, high-speed, two-path architecture of the most complex unit, the FP adder. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. The identified test conditions can be utilized with respect to any fault model and are independent of the internal structure and the size of the components. Thus, they can be applied to FP adders of various exponent and significant sizes (single, double, and custom precision), as well as to other types of FP units, which also consist of classic integer arithmetic components similarly interconnected

Weighted pseudorandom BIST schemes have been efficiently utilized in order to drive down the number of vectors required to achieve complete fault coverage in built in self test (BIST) applications. Sets of patterns comprising weights 0, 0.5 and 1 have been successfully utilized within the weighted pattern generation paradigm. In this paper an accumulator-based scheme is presented, that generates set of patterns with weights 0, 0.5 and 1. Since accumulators and ALUs are commonly found in current VLSI chips, the presented scheme can be efficiently utilized to drive down the hardware of BIST pattern generation.

High performance real number operations in embedded processors' and microprocessors' datapaths are realized by floating point (FP) arithmetic units. FP units have a complex structure which although consisting of classic integer arithmetic components faces serious testability problems due to the limited accessibility of the components from the FP unit ports. In this paper we present a test generation methodology for FP adders based on the high-speed, two-path architecture. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. According to our test methodology, the testability conditions guide test generation process. The identified test conditions are independent of the internal structure and the size of the components. Thus, they can be applied to floating point adders of various exponent and significand sizes built with components of different architectures.

Manufacturing testing is carried-out once in order to ensure the correct operation of the circuit under test right after fabrication, while either periodic off-line testing or concurrent on-line testing is carried-out in order to ensure that the circuit under test continues to operate correctly in field. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform all types of testing, namely manufacturing, periodic off-line and concurrent on-line. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing. In this paper a novel input-vector monitoring concurrent BIST scheme based on a pre-computed test set is introduced. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both on line and off-line testing

Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or-performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for embedded processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software-based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.

Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low-cost embedded systems with respect to permanent and intermittent operational faults. Such strategies are well suited to embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, information, software, or time-redundancy mechanisms. We first identify the stringent characteristics of a SBST program to be suitable for on-line periodic testing. Also, we study the probability for a SBST program to detect permanent and intermittent faults during on-line periodic testing. Then, we introduce a new SBST methodology with a new classification and test-priority scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for two pipeline reduced instruction set computers reduced instruction set processors of different architecture.

Microprocessor datapath architectures operate on signed numbers usually represented in two's-complement or sign-magnitude formats. The multiplication operation is performed by optimized array multipliers of various architectures which are often produced by automatic module generators. Array multipliers have either a standard, nonrecoded signed (or unsigned) architecture or a recoded (modified Booth's algorithm) architecture. High-quality testing of array multipliers based on a comprehensive sequential fault model and not affecting their well-optimized structure has not been proposed in the past. In this paper, we present a built-in self-testing (BIST) architecture for signed and unsigned array multipliers with respect to a comprehensive sequential fault model. The BIST architecture does not alter the well-optimized multiplier structure. The proposed test sets can be applied externally but their regular nature makes them very suitable for embedded, self-test application by simple specialized hardware which imposes small overheads. Two different implementations of the BIST architecture are proposed. The first implementation focuses on the test invalidation problem and targets robust sequential fault testing, while the second one focuses on test cost reduction (test time and hardware overhead).

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.

The detection of robustly detectable sequential faults has been extensively studied. A number of researchers have provided theoretical as well as experimental results designating that the application of single input change (SIC) pairs of test patterns results in favorable results for sequential fault testing. In this paper, a novel algorithm for the generation of SIC pairs is presented, termed Accumulator-based test generation for Robust sequential fault testing in Near-optimal time (ARN). ARN is implemented in hardware utilizing an accumulator whose inputs are driven by a barrel shifter. Since such structures are commonly found in general-purpose or specialized microprocessors or digital signal processors (DSP), the presented architecture provides a practical solution for the built-in testing of such circuits.

Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low-cost embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms. In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor.

A comprehensive online test strategy requires both concurrent and non-concurrent fault detection capabilities to guarantee SoCs's successful normal operation in-field at any level of its life cycle. While concurrent fault detection is mainly achieved by hardware or software redundancy, like duplication, non-concurrent fault detection, particularly useful for periodic testing, is usually achieved through hardware BIST. Software-based self-test has been recently proposed as an effective alternative to hardware-based self-test allowing at-speed testing while eliminating area, performance and power consumption overheads. In this paper we focus on the applicability of software-based self-test to non-concurrent on-line testing of embedded processor cores. Low-cost in-field testing requirements, particularly small test execution time and low power consumption guide the development of self-test routines. We show how self-test programs with a limited number of memory references and based on compact test routines provide an efficient low-cost on-line test strategy.

Embedded processor testing techniques based on the execution of self-test routines, have been recently proposed as an effective alternative to classical hardware Built-In Self Test. Software-based self-testing provides atspeed testing capability and does not add hardware or performance penalties. It efficiently partitions the testing task between external testers and internal processor resources. In this paper we analyze the application of a softwarebased self-testing methodology to different implementations of a complex embedded processor architecture. We demonstrate that such a methodology provides high test quality in different processor implementations with low test development and low test application costs. 1

Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex systems-on-chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. We introduce an efficient methodology for processor cores self-testing which requires knowledge of their instruction set and Register Transfer (RI) level description. Compared with functional testing methodologies proposed in the past, our methodology is more efficient in terms of fault coverage, test code size and test application time. Compared with recent software based structural testing methodologies for processor cores, our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while virtually the same fault coverage is achieved with an order of magnitude smaller test application time.

Instruction-based self-testing of embedded processor cores provides an excellent technique for balancing the testing effort for complex Systems-on-Chip (SoC) between slow, inexpensive external testers and embedded code stored in memory cores. In this paper we apply our efficient methodology for processor core self-testing based on the knowledge of its instruction set architecture and register transfer level description on a common accumulator-based processor core benchmark We also demonstrate that our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while the same fault coverage is achieved with an order of magnitude smaller test application time compared with a recently published structural methodology for processor core self-testing.

A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage without repetitive fault simulation experiments which is necessary in pseudorandom software-based processor self-testing approaches. Test generation and output analysis are performed by utilizing the processor functional modules like accumulators (arithmetic part of ALU) and shifters (if they exist) through processor instructions. No extra hardware is required and there is no performance degradation.

The modified Booth array multiplier is the most ubiquitous multiplier architecture in the datapaths of either general purpose microprocessors or specialized Digital Signal Processors. Sequential fault testing for Booth array multipliers has never been proposed in the past. In this paper, we present two BIST architectures for modified Booth array multipliers with respect to the Realistic Sequential Cell Fault model (RS-CFM). The first BIST architecture aims to resolve the test invalidation problem to the largest possible extent, while the second one aims to test cost reduction. Both BIST architectures achieve very high sequential fault coverage and impose moderate hardware and delay overhead. Simplified variations of the two BIST architectures are also presented for the non-recoded signed array multipliers. Thus, the proposed BIST architectures offer a universal BIST solution that covers the totality of signed array multipliers: non-recoded and recoded.

Power in processing cores (microprocessors, DSPs) is primarily consumed in the datapath part. Among the datapath functional modules, multipliers consume the largest amount of power due to their size and complexity. We propose a low power BIST scheme for datapaths built around multiplier-accumulator pairs. The target is low average power dissipation between successive test vectors. This is achieved by taking advantage of the regularity of multiplier modules and achieving very high fault coverage by a linear-sized test set with as small as possible input switching activity. The proposed BIST scheme is more efficient than pseudorandom BIST for the same high fault coverage target. Up to 77.2% power saving is achieved in the set of experimental results provided in the paper.

Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns. Two alternatives are proposed depending on whether the target is low energy dissipation during a BIST session or low power dissipation (i.e. average energy dissipation between successive test vectors). The proposed BIST schemes are more efficient than pseudorandom BIST for the same high fault coverage target. Up to 78.33% energy saving is achieved by the proposed low energy BIST scheme and up to 82.22% power saving is achieved by the proposed low power BIST scheme, compared with pseudorandom BIST.

Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digital circuits, like general purpose microprocessors, embedded processors, and digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become an imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test quality. In addition, it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presented. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or bilateral ILAs, with or without vertical inputs/outputs. Based on a graph model, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust test sequences. The efficiency of ILA-ATPG is demonstrated through a comprehensive set of experimental results over all classes of one-dimensional ILAs, including all practical one-dimensional ILAs, as well as a number of more complex benchmarks.

Wallace free summation in conjunction with Booth encoding are well known techniques to design fast multiplier cores widely used as embedded cores in the design of complex systems on chip. Testing of such multiplier cores deeply embedded in complex ICs requires the utilization of a BIST architecture that can be easily synthesized along with the multiplier by the module generator. In this paper we introduce an effective BIST architecture for fast multipliers that completely complies with this requirement. The algorithmic BIST patterns that this architecture generates guarantee a fault coverage higher than 99%. The required test pattern generator consists of a simple fixed-size binary counter, independent of the multiplier size. Accumulator-based compaction is adopted since multipliers and adders co-exist in most datapath architectures.

Sequential fault testing approaches for array multipliers proposed in the past target only external testing and impose significant hardware overhead due to excessive DFT modifications. In this paper we present, for the first time, a BIST architecture which does not require any DFT modifications in the multiplier structure and provides a fault coverage larger than 99% for a comprehensive sequential fault model (RS-CFM) for any multiplier size. Both robust and non-robust testing are considered. The applicability of the BIST architecture is further justified considering the case of the transistor stuck-open fault model, where a fault coverage larger than 99% is also achieved in any case.

An effective built-in self-test (BIST) scheme for parallel multipliers (array and tree) is proposed. The new scheme combines the advantages of deterministic and pseudorandom testing and avoids their drawbacks. No modifications to the multiplier structure are required. A guaranteed very high fault coverage of a comprehensive cellular fault model is achieved. The results do not depend either on the gate-level implementation of the multiplier cells or the architecture of the multiplier (whether it is a carry-propagate or carry-save array multiplier or a tree multiplier) or on the multiplier size. A small deterministic test set of highly regular test vectors is used which exploits the inherent regularity of the multiplier architecture. The regularity of the test vectors allows for their on-chip generation with a very small hardware overhead, which is equivalent to the hardware overhead of pseudorandom testing.

Traditional combinational fault models are not sufficient to detect to most common failure mechanisms in CMOS Iterative Logic Arrays (ILAs). The Realistic Sequential Cell Fault Model (RS-CFM) provides a comprehensive, robust test methodology for ILAs. It also satisfies the requirements for low test complexity and cell implementation independence. Adopting RS-CFM, we first provide sufficient conditions for two-dimensional (2D) ILAs to be robustly testable for first time in the literature. Then, we propose sufficient modifications to the carry-save and carry-propagate array multipliers so that they can be treated robustly with respect to RS-CPM with a test set of linear size.

Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic operations (like the operations of the 74/spl times/181 family) are widely used in today's complex integrated circuits, such as commercial microprocessors and digital signal processors. These ALUs are built around either ripple-carry (RC) adders, carry-lookahead (CLA) adders or mixed CLA/RC adders depending on area and performance requirements. In this paper, first, we introduce novel C-testable multifunction ALUs built around RC adders and linear-testable multifunction ALUs built around CLA adders and mined CLA/RC adders with respect to CFM. Then, we introduce an effective ALU BIST scheme for all three types of ALUs (RC, CLA, mixed CLA/RC) that hits the target of a unified datapath BIST architecture, since it is compatible to an effective BIST scheme for datapaths. Complete CFM testability is achieved with a reasonable number of deterministic test patterns in all cases. The scheme imposes reasonable area overhead and negligible delay overhead and owing to its inherent high regularity can be easily adopted for automatic BIST synthesis of datapaths.

Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs.

Datapath architectures are widely used in today's complex integrated circuits, such as commercial microprocessors or specialized digital signal processors. A very effective BIST scheme for general datapaths is introduced in this paper. This scheme requires the register transfer (RT) level description of a datapath design, since it is independent of specific implementations of the functional modules. The novel BIST scheme is generic, i.e. independent of the datapath width. Hence, it is well suited for fixed-width datapaths that suffer from testability problems due to the truncation of the low order half part of multiplications. A simplified version of the scheme can also be applied to non fixed-width datapaths. The deterministic BIST patterns applied, always guarantee more than 99% fault coverage, for the entire datapath, within few hundreds of clock cycles. This result is achieved by exploiting the inherent operational parallelism of datapaths. The scheme imposes small area overhead and near-zero delay overhead.

In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults that cause logical errors bat also faults that cause additional delays. Thus, concurrent detection, of delay faults inside the checkers is an additional application of the proposed circuit. The proposed TSC error indicator is more efficient than the TSC error indicator presented by Gaitanis (see IEEE Trans. Comput., vol. 34, no. 8, p. 753-61, 1985) which, to the authors' knowledge, is the only existing TSC error indicator in the open literature.

Array multipliers, due to their high regularity, are efficiently designed as parts of complex VLSI devices. Such embedded multipliers have low controllability and observability, making the use of appropriate BIST schemes a necessity. This paper introduces a very effective BIST scheme for carry-propagate and carry-save array multipliers. The deterministic BIST patterns produced by the Test Pattern Generator provide a fault coverage larger than 99%. The required Test Pattern Generator consists of a simple binary counter or maximum length LFSR of a fixed size (8-bits), independent of the size of the multiplier. For Output Data Evaluation a count-based scheme is adopted. The novel BIST scheme does not require any DFT in the multiplier design and is generic, i.e. independent of specific implementations of the multiplier cells.

Booth multipliers are widely used in both general purpose datapath structures and specialized Digital Signal Processors. Such multipliers when embedded in complex ICs have low controllability and observability, so the use of a suitable BIST scheme is a necessity. No Such BIST schemes for Booth multipliers are available to our knowledge in the open literature. A very effective BIST scheme for Booth multipliers is introduced. The algorithmic BIST patterns that this scheme generates guarantee >99% fault coverage. The required Test Pattern Generator consists of a simple fixed-size binary counter or maximum length LFSR, independent of the site of the multiplier. Several count-based compaction schemes are evaluated and a new such compaction scheme is found to be the most effective. The novel BIST scheme is generic, i.e., independent of specific implementations of the multiplier cells and does not require DFT in the multiplier design. Due to its effectiveness and regularity this BIST architecture was adopted for automatic BIST synthesis via the parameterized multiplier generation tool.

In this paper we give the fundamental theory for testing one or two-dimensional Iterative Logic Arrays (ILAs) with respect to realistic faults requiring two-pattern or generally n-pattern tests. We give conditions so that C-testability and linear-testability are preserved. According to our approach the extensive work made for ILAs under the Cell Fault Model can be easily used to derive an efficient test set of an ILA for more realistic faults.