This paper presents a new phenomenon called error correlation prediction for lockstep processors. Lockstep processors run the same copy of a program, and their outputs are compared at every cycle to detect divergence, and have been popular in safety-critical systems. When the lockstep error checker detects an error, it alerts the safety-critical system by putting the lockstep processor in a safe state in order to prevent hazards. This is done by running the online diagnostics to identify the cause of the error because the lockstep processor has no knowledge of whether the error is caused by a transient or permanent fault. The online diagnostics can be avoided if the error is caused by a transient fault, and the lockstep processor can recover from it. If, however, it is caused by a permanent fault, having prior knowledge about error's likely location(s) within the CPU speeds up the diagnostics process. We discover that the error's type and likely location(s) inside CPUs from which the fault may have originated can be predicted by analyzing the output signals of the CPU(s) when the error is detected. We design a simple static predictor exploiting this phenomenon and show that system availability can be increased by 42-64% with an overhead of less than 2% in silicon area and power.

Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass (Fairchild Semiconductor) planted the first seeds of using current testing as part of a structural approach to validate integrated circuits when publishing the concept of complementary-MOS (CMOS) logic circuitry. It occurred to him that a CMOS circuit would use very little power and that in standby; it would draw practically nothing — just the leakage current. It was therefore a fact that CMOS circuits with increased standby power consumption were defective. In 1981 Mark W. Levi demonstrated the concept of IDDQ testing (validating circuits by measuring and observing their quiescent supply current) in his ITC'1981 paper “CMOS is most Testable”. This paper kicked off a lot of research on IDDQ fault modeling, IDDQ defect detection capabilities, IDDQ and reliability, IDDQ efficiency. Much of that research happened in the late eighties — early nineties by “Chuck and Jerry”, exploring the benefits, followed by studies done by HP, IBM, TI, Philips, Alcatel, Ford Micro, … Since then IDDQ testing became synonym to current testing. Extensive research revealed the IDDQ capabilities. Despite its demonstrated defect detection capabilities and screening efficiency, it was not an easy way for IDDQ to make it to the production test floor. The initial lack of commercial available ATPG tools and suitable measurement solutions were the hurdles to take.

The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gate sizing technique for reducing test cost of multi-Vdddesigns with bridge defects. Using synthesized ISCAS and ITC benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves singleVddtest, without affecting the fault coverage of the original test. In addition, the proposed technique performs better in terms of timing, area, and power than the recently proposed test point insertion technique. This is the first reported work that achieves singleVddtest for resistive bridge defects, without compromising fault coverage in multi-Vdddesigns.

Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% defect coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective Gate Sizing technique for reducing test cost of multi-Vdd designs with bridge defects. Using synthesized ISCAS benchmarks and a parametric fault model, experimental results show that for all the circuits, the proposed technique achieves 100% defect coverage at a single Vdd setting; in addition it has a lower overhead than the recently proposed test point insertion technique in terms of timing, area and power.

This paper analyzes the behavior of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes. To quantify this impact, a novel metric called test robustness is proposed and to mitigate test escapes, a new process variation-aware test generation method is presented. The method exploits the observation that logic faults that have high probability of occurrence and correspond to significant amounts of undetected bridge resistance have a high impact on test robustness and therefore should be targeted by test generation. Using synthesized International Symposium on Circuits and Systems benchmarks with realistic bridge locations, results show that for all the benchmarks, the method achieves better results (less test escapes) than tests generated without consideration of process variation.

Multiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost.

This paper investigates the impact of process variation on test quality with regard to resistive bridging faults. The input logic threshold voltage and gate drives strength parameters are analyzed regarding their process variation induced influence on test quality. The impact of process variation on test quality is studied in terms of test escapes and measured by a robustness metric. It is shown that some bridges are sensitive to process variation in terms of logic behavior, but such variation does not necessarily compromise test quality if the test has high robustness. Experimental results of Monte-Carlo simulation based on recent process variation statistics are presented for ISCAS85 and -89 benchmark circuits, using a 45 nm gate library and realistic bridges. The results show that tests generated without consideration of process variation are inadequate in terms of test quality, particularly for small test sets. On the other hand, larger test sets detect more of the logic faults introduced by process variation and have higher test quality.

Multiple-voltage is an effective dynamic power reduction design technique, commonly used in low power ICs. To the best of our knowledge there is no reported work for diagnosing multiple-Vdd enabled ICs and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. Using synthesized ISCAS benchmarks, with realistic extracted bridges and parametric fault model; the paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multi-Vdd diagnosis algorithm.

One effective fault injection approach involves instrumenting the RTL in a controlled manner to incorporate fault injection, and evaluating the behaviour of the faulty RTL whilst running some benchmark programs. This approach relies on checking the effects of faults whilst the design is executing a specific binary image, and therefore the true impact of the fault is limited by the shadow of the program image. Another limitation of this approach is the use of extra hardware for fault injection which is not needed during the fault-free running of the design. The aim of this paper is to propose a new approach for transient fault injection based on symbolic simulation and model checking that circumvents the problems experienced due to application dependent fault injection and RTL modification. In this paper we present our approach and analyse the effect of transient faults on the fetch unit of a 32-bit multi-cycle RISC processor. Our approach can be applied generally to any faulty design, not necessarily a processor.

A key design constraint of circuits used in hand-held devices is the power consumption, mainly due to battery-life limitations. Adaptive power management (APM) techniques aim at increasing the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems; however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi- automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits.

A key design constraint of circuits used in handheld devices is the power consumption, due mainly to the limitations of battery life. The employment of adaptive power management (APM) methods optimizes the power consumption of such circuits. This paper describes an effective APM-aware DFT technique that consists of a Test Generation Suite, including fault list generation, test pattern generation and fault simulation. The test generation suite is capable of generating test patterns for multiple supply voltage (Vdd) settings to maximize coverage of resistive bridging faults; and a method to reduce the number of Vdd settings without compromising the fault coverage in order to reduce the cost of test. Preliminarily validations of the proposed DFT technique using a number of benchmark circuits demonstrate its effectiveness.

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover.

While the IEEE P1500 standards working group is on the verge of recommending a standard test interface for non-mergeable cores, a need was felt to adopt a standard methodology to achieve easy test interoperability for non-merged core (RTL, gate level) integration. A task force was formed under the P1500 working group investigating this issue and came up with a recommendation. DFT Disclosure Document (DDD) was the outcome of this exercise. The DDD, targeted to be an IEEE standard recommended practice document, aims at capturing the DFT related experience the core provider would like to share with the integrator to facilitate easy test integration. This paper presents the objective and structure of this document along with some use models from participating companies as well as an example.

This paper discusses the test strategies that can be employed for testing reusable Intellectual Property (IP). A typical System on Chip (SoC) design carried out at ARM is presented as a case study. It highlights the challenges faced when integrating IP blocks from diverse sources. A hybrid approach was found to be the most pragmatic solution, mixing bus-based, functional, scan and at-speed testing. The paper concludes with a look at how the task of resting reusable IP will benefit from industry standardisation efforts.