Wireless Sensor Networks are nowadays employed in several applications. Cyber-physical systems, health-care instruments and Internet of Things are using hundreds of smart sensors, which include also processing capability together with sophisticated communication protocols. The presence of faults in these critical applications must be checked during runtime, to detect transient and permanent faults that could seriously affect the entire system dependability and endanger human users. Continuous checking has been proven as inefficient in many cases, due to the low degrees of observability and controllability and to the limited life time of batteries. Even, on-line testing is often unable to report the presence of internal errors, which can remain latent during long times. In this paper, a proposal is presented for improving the on-line testability of the different type of nodes in a WSN, saving energy and tracking error from their origin.

Approximate logic circuits can be used in hardware redundancy approaches to reduce the overheads at the expense of slightly sacrificing robustness. However, a major drawback of existing logic approximation methods lies in the difficulty of estimating the effect of approximations in the total error probability and therefore to identify and select optimal approximation transformations. In this work, we propose an approach to build approximate logic circuits for a given acceptable error target. Using signal probabilities, we can dynamically estimate the probability of error that can be expected when an approximation is taken, use it to iteratively select optimal transformations and keep an estimation of the total error probability in order to stick to a given target. Experimental results show how this approach can be used to generate optimal approximate logic circuits for any particular tradeoff between robustness and area overhead.

Permanent faults (e.g., due to electronic components aging) represent a real problem in nowadays digital systems working in automotive vehicles. Mandatory tests should be done at the vehicle key-on in order to detect damaged elements. Generation and validation of these tests can be improved in a great manner considering the characteristics of the target distributed subsystems. In this work, an approach for in-field detection of permanent faults in a LIN network is proposed.

Robust communications protocols are widely used in safety critical applications, such as aerospace or automotive systems. On-board complex systems, working in harsh environments, are composed of distributed modules with a high degree of interaction and critical tasks replication. Single Event Upsets (SEUs) are very probable to affect these modules and their communications. Robust protocols are usually designed to correct communication data errors, usually due to problems in the physical medium (e.g. noise). They provide robustness in data transmission but fault tolerance is not ensured in the interface control logic. In this work, a study of the SEU sensitivity of a typical robust communication protocol, the CAN bus, is performed. Authors have applied an extensive fault injection campaign in the internal modules of the circuit that implements this standard in order to perform a depth analysis. Experimental results prove robustness is not complete in the control part of this protocol. Selective hardening will enhance this robustness with low extra cost in terms of area or performance.

Logic masking approaches for Single-Event Transient (SET) mitigation use hardware redundancy to mask the propagation of SET effects. Conventional techniques, such as Triple-Modular Redundancy (TMR), can guarantee full fault coverage, but they also introduce very large overheads. Alternatively, approximate logic circuits can provide the necessary flexibility to find an optimal balance between error coverage and overheads. In this work, we propose a new approach to build approximate logic circuits driven by testability estimations. Using the concept of unate functions, approximations are performed in lines with low testability in order to minimize the impact on error coverage. The proposed approach is scalable and can provide a variety of solutions for different trade-offs between error coverage and overheads.

Estimation of soft error sensitivity is crucial in order to devise optimal mitigation solutions that can satisfy reliability requirements with reduced impact on area, performance, and power consumption. In particular, the estimation of Single Event Transient (SET) effects for complex systems that include a microprocessor is challenging, due to the huge potential number of different faults and effects that must be considered, and the delay-dependent nature of SET effects. In this paper, we propose a multilevel FPGA emulation-based fault injection approach for evaluation of SET effects called AMUSE (Autonomous MUltilevel emulation system for Soft Error evaluation). This approach integrates Gate level and Register-Transfer level models of the circuit under test in a FPGA and is able to switch to the appropriate model as needed during emulation. Fault injection is performed at the Gate level, which provides delay accuracy, while fault propagation across clock cycles is performed at the Register-Transfer level for higher performance. Experimental results demonstrate that AMUSE can emulate soft error effects for complex circuits including microprocessors and memories, considering the real delays of an ASIC technology, and support massive fault injection campaigns, in the order of tens of millions of faults within acceptable time.

The process of designing robust digital systems is getting heavier and longer due to the increase of functional complexity and circuit sensitiveness [1][2]. Furthermore, aerospace and automotive electronics are including more digital systems with critical tasks distribution among several single and cheaper modules. Although collaborative hardening is providing very interesting results in terms of cost and reliability, the design process becomes more difficult. Redundant tasks, hardware and software, must be evaluated together with the global and local error mitigation techniques. Also, network links affect error propagation and mitigation. Finally, the error accumulation must be considered in these systems working in harsh conditions. In this paper we present a general method for evaluating the Single Bit Upsets (SBU) sensitivity of complex digital systems with critical tasks distribution and collaborative hardening. This method performs a detailed analysis of signal integrity along system operation thanks to hardware emulation in the early steps of the design cycle.

In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

An increasing number of applications require being able to detect possible faults arising during the normal activity of the electronic system: for this reason, on-line fault detection is a hot topic today. This paper proposes a new technique which is suitable for microprocessor-based systems (no matter whether they are implemented in a single device or with discrete COTS) that exploit hardware duplication and combines it with the On-Chip Debug features existing in many processors. The new technique increases the observability of faults (thus increasing detection probability and reducing latency) and is characterized by a very reduced intrusiveness in terms of changes required in the application code.

SEU effects are a main concern in an increasing number of applications. Selective hardening in early design stages is intended to design a robust circuit in a fast and cost-efficient way. In this paper, a method to performing selective hardening in digital circuits against SEUs is described. This method is based on the autonomous emulation fault injection technique. It allows the designer to identify the critical parts of the circuit and use different hardening techniques to reach a trade-off between the obtained robustness and area and performance penalties. A PIC microcontroller has been analysed in detailed against SEU effects as case study, injecting millions of faults. Results points out that hardening just 17% of the circuit flip-flops reduces the failure rate induced by SEUs in 99%.

Latest mitigation techniques proposed at register-transfer level for dependable cryptosystems deal with time redundancy in an active on-line error-detection scheme. Round-based block ciphers are very likely to be hardened with these techniques. Although good results are achieved in terms of area or time overhead, intentional attacks are still able to obtain crucial information by means of intensive fault injection campaigns. In this paper, a new solution is presented and analyzed, dealing with pseudo-random number generators (PRNG) with the goal of misleading attackers and, therefore, making cryptosystem more robust. With this approach, attackers must face two difficulties: dealing with on-line error detection and ignoring the fault location in the round sequence. PRNG will produce different repetition sequences for the rounds of the cryptosystem, making very difficult to correlate output data with injected faults.

We propose an approach to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.

Encryption algorithms could suffer fault injection attacks in order to obtain the secret key. In this paper, a specific protection for any round-based encryption algorithm is presented, analyzed and tested. It is providing a high degree of robustness together with a small penalty in the algorithm throughput when dealing with specific intentional attacks. Experimental results on Advanced Encryption Standard are presented and discussed.

Processors are very common components in current digital systems and to assess their reliability is an essential task during the design process. In this paper a new fault injection solution to measure SEU sensitivity in processors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). It can be widely applicable to different processors since JTAG standard is an extended interface and OCDs are usually available in current processors. The hardware implementation avoids the communication between the target system and the software debugging tool. The method has been applied to a complex processor, the ARM7TDMI. Results illustrate the approach is a fast, efficient and cost-effective solution.

FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed autonomous emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the autonomous emulation techniques to circuits with embedded memories is presented. The LEON2 processor benchmark is used to demonstrate as an application for the proposed techniques

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitivity to radiation. So errors are currently appearing in ICs working at the Earth's surface. Hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. The use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the FT evaluation. In this work, a new emulation system for FT evaluation with respect to SEU effects is proposed, providing shorter evaluation times by performing all the evaluation process in the FPGA and avoiding emulator-host communication bottlenecks.

Platform FPGAs provide a high degree of reconfigurability and a high density of integration. These features make these devices very suitable for hardware emulation and in particular for fault tolerance evaluation. There are several FPGA-based approaches that enhance notably the fault tolerance evaluation process achieving an important speed up. However, such methods are limited by the communication between the FPGA and the host computer, which manages the emulation process. In order to minimize this communication and therefore accelerate the overall process, an autonomous emulation system is proposed in this paper. This solution profits from additional hardware resources available in current platform FPGAs such as embedded RAM. In the proposed system, a complete emulation campaign and its management is embedded in the FPGA, accelerating emulation process up to two orders of magnitude without losing flexibility with respect to other hardware solutions.

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Therefore, hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. The use of CAD tools, for the generation and the validation of fault tolerant circuits, will allow designers to obtain hardened devices in a cost-effective way with short development times and with high reliability results. While automatic insertion of fault tolerant structures in designs is already possible, automatic evaluation with an optimum time-cost relation is still needed. In this sense, the use of platform FPGAs for the emulation of single-event upset effects (SEU) is gaining attention in order to speed up the fault tolerance evaluation. In this work, a new emulation system for the evaluation of FT with respect to SEU effects is proposed. This solution gets profit of hardware resources for accelerating the FT evaluation. It is analysed and compared with respect to other emulation techniques. The proposed solution provides not only short times but also low cost in area for FT validation, giving better results than pure software or hardware solutions.