Major Advantages of IPUs Separation of Infrastructure & Tenant Guest can fully control the CPU with their SW, while CSP maintains control of the infrastructure and Root of Trust Infrastructure Offload Accelerators help process these task efficiently. Minimize latency and jitter and maximize revenue from CPU Diskless Server Architecture Simplifies data center architecture while adding flexibility for the CSP

Modern distributed memory parallel computers provide hardware support for the efficient and reliable delivery of interprocessor messages. This facility needs to be accessed by lightweight protocols that do not waste the performance of the underlying hardware; the heavyweight layering techniques traditionally used in distributed systems are wholly inappropriate. A low-level communication interface is therefore presented which exploits modern architectures effectively, while maintaining a good match to existing parallel programming environments. The interface defines mechanisms to access an asynchronous reliable packet delivery service. It permits messaging protocols to be efficiently synthesized by considering the activity at their end-points alone. This arrangement effectively decouples the implementation of protocols from low-level architectural features, and hence aids the portability of parallel programming environments. Furthermore, the interface allows the communication network to be shared by multiple programming paradigms, giving additional flexibility over existing systems.>

Abstract Modern multicomputer components such as the inmos T800 and the Texas Instruments TMS320C40 provide hardware which supports efficient communication between directly connected processors. The paper describes techniques which have been developed to provide efficientglobalcommunications for machines based on these and similar processors. This service is implemented by a packet‐routing kernel adopting a standard, portable communications interface. The design of this kernel is discussed with particular emphasis on the manner in which it guarantees reliable, lightweight, deadlock‐free communication for arbitrary interconnection topologies. The kernel has been developed and tested on transputers. Extensive results on the performance of the router are presented to demonstrate that the substantial advantages associated with its well founded, structured design are not at odds with high efficiency. This router has been used to support several multi‐transputer environments, including a commercially available POSIX‐conformant operating system and a distributed occam environment freed from conventional configuration constraints.