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R. Janow

dblp:79/3992 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1990
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
neural network hardware		 0.011990
Reconfigurable Neural Net Chip with 32K Connections · NIPS 1990
Hardware accelerators and domain-specific architectures
neural network implementation		 0.011990
Reconfigurable Neural Net Chip with 32K Connections · NIPS 1990
YearPublicationVenuePosition
1990 Reconfigurable Neural Net Chip with 32K Connections
Hans Peter Graf, R. Janow, Donnie Henderson
 NIPS2