We propose a systematic pipelining method for a linear system to minimize power and maximize throughput, given a constraint on the number of pipeline stages and a set of resource constraints. Unlike most existing pipelining approaches, our method takes the number of pipeline stages as one of the constraints and considers the pipelining as an aspect of power minimization. Operations are retimed so that as many operations as possible take common operands as their inputs, using a novel technique called force-directed retiming; operand sharing is then determined, based on list scheduling. Experimental results show that the proposed approach reduces the power consumption of functional units by 27.8% on average and by more than 50% in some cases, compared to the state-of-the-art pipelining and operand sharing techniques.

As process technology goes into deep submicron range, interconnect delay becomes dominant among overall system delay, occupying most of the system clock cycle time. Interconnect delay is now a crucial factor that needs to be considered even during high-level synthesis. In this paper, we propose a concurrent scheduling and binding algorithm that takes interconnect delay into account. We first define our distributed target architecture, which minimizes the effect of interconnect delay on clock cycle time. We no longer assume that interconnect delay between functional units is a part of one clock cycle. Interconnect delay can span over multiple clock cycles. We incorporate the concept of multi-cycle interconnect delay into scheduling and binding process, to reduce the critical path length and therefore the system latency. We show that by introducing interconnect delay, we can obtain latency improvement of up to 54 % and of 37% on the average.

Interconnect delay should be considered together with computation delay during architectural synthesis in order to achieve timing closure in deep submicrometer technology. In this paper, we propose an architectural synthesis technique for distributed-register architecture, which separates interconnect delay for data transfer from component delay for computation. The technique incorporates performance-driven placement into the architectural synthesis to minimize performance overhead due to interconnect delay. Experimental results show that our methodology achieves performance improvement of up to 60% and 22% on the average.

Article Low power pipelining of linear systems: a common operand centric approach Share on Authors: Daehong Kim EECS, Seoul National University, Seoul, Korea EECS, Seoul National University, Seoul, KoreaView Profile , Dongwan Shin ICS, UC Irvine ICS, UC IrvineView Profile , Kiyoung Choi EECS, Seoul National University, Seoul, Korea EECS, Seoul National University, Seoul, KoreaView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 225–230https://doi.org/10.1145/383082.383141Online:06 August 2001Publication History 9citation224DownloadsMetricsTotal Citations9Total Downloads224Last 12 Months3Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Providing multiple modes to support dynamically changing environments, standards, and new services is prevalent in embedded systems, especially in mobile radio systems. Because such a system frequently contains time-constrained tasks, it is important to analyze the temporal requirements as well as the functional correctness. This paper presents a method to analyze temporal requirements imposed on an embedded real-time system supporting multiple modes. While most performance analysis methods focus only on testing the feasibility of a task or a system, our method goes further by addressing the problem of locating hot spots of a system thereby helping the designer to choose among alternative designs or architectures. We formally define the analysis problem and show that it is very unlikely to be solved efficiently. We present a heuristic algorithm, which is accurate and fast enough to be used in iterative processes in system-level analysis and design. The analysis problem is extended to accommodate probabilistic behavior exhibited by soft real-time tasks.

In this paper, a transformation technique, called powerconscious loop folding is proposed for high level synthesis of a low power system. Our work is focused on reducing the power consumed by functional units through the decrease of switching activity in a data path dominated circuit containing loops. The transformation algorithm has been implemented and integrated into a high level synthesis system for experiments. In our experiments, we could achieve power reduction of up to 50% for circuits dominated by functional units. 1. Introduction Until 1980's, one of the most important factors that determined the quality of a system was the speed and so much effort had been made to increase the speed at a minimal cost or silicon area. But, in 1990's, as the portable system market grows rapidly and reliability problems due to high power dissipation are becoming an issue for systems operating in high clock frequency, low power design is becoming more and more important and is now one of the m...