Solar power generation has attracted significant attention recently as a safe and environmentally friendly renewable energy source. However, generally speaking, since the service lives of solar power systems are relatively long, and since it is difficult to detect anomalies in individual solar panels, such plants tend to operate without much consideration for individual panel anomalies. In order to more comprehensively monitor solar power generation systems, the National Institute of Advanced Industrial Science and Technology (AIST) of Japan has developed a direct current (DC) power line communication system that enables monitoring of each panel in a system. Monitored data are then integrated and uploaded to the cloud. Using this monitored data, we found that the integrated power ratio trends of single panel power output are in accordance with a normal distribution. Therefore, herein, we propose an anomaly detection method that uses a normal distribution. We then describe an experiment using 24 solar panels into which pseudo-faults were induced and show that our proposal makes it possible to detect errors with high accuracy.

This paper describes the GRD (Genetic Reconfiguration of DSPs) chip, which is evolvable hardware designed for neural network applications. The GRD chip is a building block for the configuration of a scalable neural network hardware system. Both the topology and the hidden layer node functions of a neural network mapped on the GRD chips are dynamically reconfigured using a genetic algorithm (GA). Thus, the most desirable network topology and choice of node functions (e.g., Gaussian or sigmoid function) for a given application can be determined adaptively. This approach is particularly suited to applications requiring the ability to cope with time-varying problems and real-time constraints. The GRD chip consists of a 100 MHz 32-bit RISC processor and 15 33 MHz 16-bit DSPs connected in a binary-tree network. The RISC processor is the NEC V830 which executes mainly the GA. According to chromosomes obtained by the GA, DSP functions and the interconnection among them are dynamically reconfigured. The GRD chip does not need a host machine for this reconfiguration. This is desirable for embedded systems in practical industrial applications. Simulation results on chaotic time series prediction are two orders of magnitude faster than on a Sun Ultra 2.

In contrast to conventional hardware where the structure is irreversibly fixed in the design process, evolvable hardware (EHW) is designed to adapt to changes in task requirements or changes in the environment, through its ability to reconfigure its own hardware structure dynamically and autonomously. This capacity for adaptation, achieved by employing efficient search algorithms based on the metaphor of evolution, has great potential for the development of innovative industrial applications. This paper introduces EHW chips and six applications currently being developed as part of MITI's Real-World Computing Project; an analog EHW chip for cellular phones, a clock-timing architecture for Giga hertz systems, a neural network EHW chip capable of autonomous reconfiguration, a data compression EHW chip for electrophotographic printers, and a gate-level EHW chip for use in prosthetic hands and robot navigation.

This paper describes an image compression system based on evolvable hardware (EHW) for high precision printers (HPP). These printers are especially flexible for book publishing, but require large disk space for images, in particular those of higher resolution. To increase the printing speed and reduce the disk space, the images should be compressed. The system for this compression must be (1) adaptive, so that it changes depending on image characteristics and (2) on-line, which means implemented in hardware. The standard compression methods have a simple template change strategy which is not efficient for the images of HPP. We used an EHW system for compressing HPP images in real time. The EHW is a type of adaptive hardware which allows evolutionary algorithms to change the hardware configuration in real time. It works as fast as other compression systems (like the JBIG standard), but changes the image modeling to reflect the changes in the image characteristics. Simulation results show more than a 50% increase in compression ratio compared to JBIG for the printer system.

Great interest has been shown in the application of the principles of artificial life to physically embedded systems such as mobile robots, computer networks, home devices able continuously and autonomously to adapt their behavior to changes of the environments. At the same time researchers have been working on the development of evolvable hardware, and new integrated circuits that are able to adapt their hardware autonomously and in real time in a changing environment. This article describes the navigation task for a real mobile robot and its implementation on evolvable hardware. The robot must track a colored ball, while avoiding obstacles in an environment that is unknown and dynamic. Although a model-free evolution method is not feasible for real-world applications due to the sheer number of possible interactions with the environment, we show that a model-based evolution can reduce these interactions by two orders of magnitude, even when some of the robot's sensors are blinded, thus allowing us to apply evolutionary processes online to obtain a self-adaptive tracking system in the real world, when the implementation is accelerated by the utilization of evolvable hardware.