A SAR architecture is proposed that employs a predictive technique to increase the conversion speed. In this new technique, the comparator operates in parallel with the logic and DAC, reducing the SAR timing budget per cycle to only one comparator decision time plus its clock generation. Moreover, a clock and input signal distribution method is presented that improves clock phase matching in a time-interleaved system. This is accomplished by delivering the primary clock to each channel and generating their interleaved phases locally. Realized in 28-nm CMOS technology, a 6-bit 10-GS/s 17.6-mW prototype achieves an SNDR of 31.2 dB at an input frequency of 4.96 GHz and a figure of merit equal to 59 fJ per conversion step.

Wireline links present various circuit stages in the signal path, requiring sufficient bandwidth so as to contribute negligible intersymbol interference. This paper analyzes the effect of circuit bandwidth limitations on NRZ and PAM4 waveforms and quantifies the necessary excess bandwidth when the data format is changed from the former to the latter so as to double the data rate. It is observed that the PAM4 eye width is particularly sensitive, demanding at least a fourfold increase in the bandwidth.

A methodology is proposed for the optimum design of on-chip transmission lines carrying high-speed clocks. Differential metal 9 or stacked metal 8/metal 9 geometries with no ground plane emerge as best choices. Moreover, CMOS and CML signaling schemes are compared for clock distribution. It is shown that CMOS clocks are better suited for frequencies up to 20 GHz and line lengths up to 5 mm.

High-speed wireline transceivers and analog-to-digital converters are sensitive to broadband phase noise of their clocks. It is generally assumed that the total rms jitter can be computed by integration of the phase noise profile up to the Nyquist rate. This paper shows that the integration limits depend on the measurement or simulation environment and, in some cases, must be chosen equal to twice the Nyquist rate.

The integral nonlinearity of digital-to-analog converters manifests itself as adjacent-channel power in RF transmitters. This paper derives compact equations relating these two quantities and verifies the results by simulations. Both current-steering and switched-mode architectures are analyzed.

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.

This paper formulates the jitter-power trade-offs in the design of phase-locked loops that provide the sampling clock for ADCs. We obtain lower bounds for the oscillator power consumption in terms of the performance penalty allowed for the ADC. We show that the oscillator power grows with the square of the target signal-to-noise ratio and the square of the clock frequency and is expected to exceed that of the ADC in future designs.

A new method of analyzing the effect of charge pump mismatches upon the phase noise of ΣΔ fractional-N synthesizers is proposed. This approach produces a simple, universal relationship between the mismatch and the ratio of the noise floor to the peak of the quantization noise spectrum. Simulations confirm that the ratio is relatively independent of other synthesizer parameters such as the ΣΔ modulator order, the shape of the spectrum, and the maximum phase excursion at the feedback divider output.

The average smart phone user picks up the device 1,500 times a week. Wireless communication appears to be taking over our lives but it also presents interesting challenges to RF designers. This paper contends that the mobile terminal will emerge as a central command post for most of our daily affairs and will therefore sustain an increasingly heavier load in terms of speed, power dissipation, and cost. Low-voltage, low-power universal radios will thus become an essential component to meet future communication demands.

The RF design paradigm will change significantly as CMOS technology scales and integration levels rise to accommodate multi-band, multi-mode transceivers and baseband processors. This paper describes technology scaling issues such as low supply voltages, high gate leakage currents, and low transistor output impedances. Also, design techniques for low-voltage mixers are presented, and stacked and nested inductors are proposed to achieve compact layouts for multi-band systems.

The integration of millimeter-wave transceivers in CMOS technology can benefit from sophisticated signal processing and calibration techniques already is use at lower frequencies. This paper describes a CMOS heterodyne receiver with on-chip LO and frequency divider that achieves a noise figure of 6.9-8.3 dB while consuming 80 mW. A frequency divider is also presented that operates from 64 to 70 GHz in 0.13-μm CMOS technology with a power dissipation of 6 mW.

This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the first implementation incorporates a ring oscillator and a linear phase detector whereas the second implementation uses a multiphase LC oscillator and a bang-bang phase/frequency detector. Fabricated in 0.18-μm CMOS technology, the power consumption of each of the circuits is less than 100˜mW. The rms jitter of the output clock for the two prototypes is 1˜ps and 0.8˜ps, respectively, while the latter achieves a capture range of more than 14%.

This paper describes the challenges in designing RF integrated circuits for wireless transceiver applications. Receiver architectures such as heterodyne, homodyne, and image-reject topologies are presented and two transmitter architectures, namely, one-step and two-step configurations are studied. The design of building blocks such as low-noise amplifiers, mixers, and oscillators is also considered.