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Clem Dickey

dblp:79/6042 · also Clement L. Dickey · DBLP profile ↗
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7ranked-venue papers
0as first author
2since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 since 2021Software engineering, systems software and programming languages · 2 · 1 since 2021Databases, data management, data science and information retrieval · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Memory systems · 58% Storage systems · 40% Processor architecture and microarchitecture · 2%

Topics — the 6 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › non-volatile memory
phase change memory
0.422014
Evaluating Phase Change Memory for Enterprise Storage Systems: A Study of Caching and Tiering Approaches · ACM Trans. Storage 2014
Evaluating phase change memory for enterprise storage systems: a study of caching and tiering approaches · FAST 2014
Storage systems › storage architecture
enterprise storage
0.212014
Evaluating phase change memory for enterprise storage systems: a study of caching and tiering approaches · FAST 2014
Memory systems
non-volatile memory
0.212014
Evaluating phase change memory for enterprise storage systems: a study of caching and tiering approaches · FAST 2014
Memory systems › cache management
storage caching
0.212014
Evaluating Phase Change Memory for Enterprise Storage Systems: A Study of Caching and Tiering Approaches · ACM Trans. Storage 2014
Storage systems › storage hierarchy
tiered storage
0.212014
Evaluating Phase Change Memory for Enterprise Storage Systems: A Study of Caching and Tiering Approaches · ACM Trans. Storage 2014
Processor architecture and microarchitecture
chip multiprocessor
0.012008
Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling · FAST 2008

Methods — techniques the papers use, named apart from their topics

workload trace analysis · 0.2performance study · 0.2
YearPublicationVenuePosition
2022 A case for using cache line deltas for high frequency VM snapshotting
abstract
Active-standby schemes for Virtual Machine (VM) high availability require periodic synchronization of memory and CPU state. The most common approach to synchronization is to use page tables and software to identify "dirty" memory pages at the source and in turn copy them to the target via a network or interconnect. However, this approach results in significanct page table traversal and data copying overhead, resulting in considerable VM downtime. A principal contributor to this overhead is that many applications using this approach incur data copy-amplification as a result of copying more data than is necessary; this arises because of the processor's virtual memory system design in which memory pages are 4KiB or larger.
Daniel G. Waddington, Moshe Hershcovitch, Swaminathan Sundararaman, Clem Dickey
SoCC4
2021 PyMM: Heterogeneous Memory Programming for Python Data Science
abstract
While persistent memory (PMEM) is a promising technology, leveraging it with legacy applications is non-trivial. This is primarily because legacy applications assume all memory is volatile and there is no notion of crash-consistency or state recovery. As new types of persistent and intelligent memory emerge, propelled by the CXL standard, the problem of integration and adoption remains.
Daniel G. Waddington, Moshe Hershcovitch, Clem Dickey
PLOS@SOSP3
2020 Evaluating Intel 3D-Xpoint NVDIMM Persistent Memory in the Context of a Key-Value Store
abstract
Intel's 3D-Xpoint NVDIMM product1 is now in general availability. This technology, herein termed Optane-PM, is a first-in-breed persistent memory technology, designed for the enterprise storage domain. Optane-PM is attached to the memory-bus and is load-store addressable. It provides higher capacity and density than DRAM, while also enabling non-volatility - data is persistent and durable across power-cycles. This paper presents a detailed evaluation of adopting Optane-PM in key-value stores. To achieve this goal, we designed and implemented a high-performance, memory-centric key-value store (MCKVS), that directly leverages persistent memory for data and meta-data storage. Multiple storage back-ends, with different software stacks, are used to provide a comparative analysis and help us understand how Optane-PM is positioned on the performance landscape. We also conducted comparisons against popular in-memory KV stores based on DRAM.
Daniel G. Waddington, Clem Dickey, Luna Xu, Travis Janssen, Jantz Tran, Kshitij A. Doshi
ISPASS2
2014 Evaluating phase change memory for enterprise storage systems: a study of caching and tiering approaches
Hyojun Kim, Sangeetha Seshadri, Clem Dickey, Lawrence Chiu
FAST3
2014 Evaluating Phase Change Memory for Enterprise Storage Systems: A Study of Caching and Tiering Approaches
abstract
Storage systems based on Phase Change Memory (PCM) devices are beginning to generate considerable attention in both industry and academic communities. But whether the technology in its current state will be a commercially and technically viable alternative to entrenched technologies such as flash-based SSDs remains undecided. To address this, it is important to consider PCM SSD devices not just from a device standpoint, but also from a holistic perspective. This article presents the results of our performance study of a recent all-PCM SSD prototype. The average latency for a 4KiB random read is 6.7μs, which is about 16× faster than a comparable eMLC flash SSD. The distribution of I/O response times is also much narrower than flash SSD for both reads and writes. Based on the performance measurements and real-world workload traces, we explore two typical storage use cases: tiering and caching. We report that the IOPS/$ of a tiered storage system can be improved by 12--66% and the aggregate elapsed time of a server-side caching solution can be improved by up to 35% by adding PCM. Our results show that (even at current price points) PCM storage devices show promising performance as a new component in enterprise storage systems.
Hyojun Kim, Sangeetha Seshadri, Clem Dickey, Lawrence Chiu
ACM Trans. Storage3
2010 Automated lookahead data migration in SSD-enabled multi-tiered storage systems
abstract
The significant IO improvements of Solid State Disks (SSD) over traditional rotational hard disks makes it an attractive approach to integrate SSDs in tiered storage systems for performance enhancement. However, to integrate SSD into multi-tiered storage system effectively, automated data migration between SSD and HDD plays a critical role. In many real world application scenarios like banking and supermarket environments, workload and IO profile present interesting characteristics and also bear the constraint of workload deadline. How to fully release the power of data migration while guaranteeing the migration deadline is critical to maximizing the performance of SSD-enabled multi-tiered storage system. In this paper, we present an automated, deadline-aware, lookahead migration scheme to address the data migration challenge. We analyze the factors that may impact on the performance of lookahead migration efficiency and develop a greedy algorithm to adaptively determine the optimal lookahead window size to optimize the effectiveness of lookahead migration, aiming at improving overall system performance and resource utilization while meeting workload deadlines. We compare our lookahead migration approach with the basic migration model and validate the effectiveness and efficiency of our adaptive lookahead migration approach through a trace driven experimental study.
Gong Zhang 0008, Lawrence Chiu, Clem Dickey, Ling Liu 0001, Paul Muench, Sangeetha Seshadri
MSST3
2008 Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling
Sangeetha Seshadri, Lawrence Chiu, Cornel Constantinescu, Subashini Balachandran, Clem Dickey, Ling Liu 0001, Paul Muench
FAST5