In this paper, we propose a novel data hiding algorithm for high dynamic range (HDR) images encoded by the OpenEXR file format. The proposed algorithm exploits each of three 10-bit mantissa fields as an embedding unit in order to conceal k bits of a secret message using an optimal base which produces the least pixel variation. An aggressive bit encoding and decomposition scheme is recommended, which offers a high probability to convey (k + 1) bits without increasing the pixel variation caused by message concealment. In addition, we present a bit inversion embedding strategy to further increase the capacities when the probability of appearance of secret bit “1” is greater than 0.5. Furthermore, we introduce an adaptive data hiding approach for concealing more secret messages in pixels with low luminance, exploiting the features of the human visual system to achieve luminance-aware adaptive data hiding. The stego HDR images produced by our algorithm coincide with the HDR image file format, causing no suspicion from malicious eavesdroppers. The generated stego HDR images and their tone-mapped low dynamic range (LDR) images reveal no perceptual differences when subjected to quantitative testing by visual difference predictor. Our algorithm can resist steganalytic attacks from the HDR and LDR RS and SPAM steganalyzers. We present the first data hiding algorithm for OpenEXR HDR images offering a high embedding rate and producing high visual quality of the stego images. Our algorithm outperforms the current state-of-the-art works.

As a result of the explosive growth in development for computer networks and information technologies in recent years, various activities take place on the Internet, such as the multimedia services. Today, the distribution of large scale digital content (such as audio, video and images) has become easier and more efficient than ever before. However, the intellectual property violation of copyright‐protected content has emerged as a major concern. Therefore digital contents are generally encrypted to prevent unauthorised access. A technology of digital rights management (DRM) refers to any of several encryption technologies used to protect digital contents against unauthorised copying, and to control the distribution of the content. Recently, Zhang et al . proposed a DRM authentication scheme based on smart card to realise session key exchange and mutual authentication among all the parties in DRM environment. The proposed scheme is efficient at server side and compact in smart card design. However, the authors will show their proposed scheme cannot resist insider attack and stolen smart card attack, then the authors will propose an improved scheme to preclude above weaknesses.

In this paper, we investigate the effect of packet aggregation on the delay performance of the IEEE 802.11 Point Coordination Function (PCF) MAC. We intend to use packet aggregation to reduce polling overhead of 802.11 PCF and improve the delay performance. We consider two different polling schemes for assembling variable-length packets for transmission: poll once and multiple poll. An analytical model is developed for evaluating the queueing delay of packets at nodes using 802.11 PCF MAC for medium access. Based on this model, we derive several closed-form expressions for computing average delay and queue length. To verify the correctness of our analytical model, we also develop a simulator for the 802.11 PCF MAC. The simulation results well match the analytical results. Several quantitative examples are given for illustrating the reduced average delays under various load conditions and limits of aggregated frames. We find that the average delay decreases with the limit of aggregated frames. We also find that, between the two polling schemes, the multiple-poll scheme achieves a smaller average delay and queue length.

Because of the lack of random access memory in optical domain, optical buffering implemented by fiber delay lines is currently a main way. Typical optical buffering architecture falls into two categories: feed-forward and feedback buffering. Both have advantages and disadvantages. In this paper, we propose an effective hybrid buffering architecture based on output-buffered feed-forward and feedback shared buffering architecture. The proposed architecture employs feed-forward output buffers to connect packets to form a variable-length frame, and employs a feedback shared buffer with a large storage frame to handle frames behind feed-forward output buffers. This scheme uses a frame concept to reduce the control complexity and increase the buffer depth. Our simulation results show that the proposed architecture improves the switch performance and outperforms an existing hybrid buffering architecture, partially shared buffering architecture, in terms of packet loss probability.

The coverage problem for targets with directional sensor nodes has been studied in this paper. To improve the coverage rate for targets, we propose a Weighted Centralized Greedy Algorithm (WCGA). The weight function added in the WCGA could be adjusted according to different density of sensor nodes in directional sensor networks. A serious of experiments have been performed to evaluate the performance of the proposed method. Simulation results show the improvement of the target coverage rate and the effectiveness of the proposed method.

This work analyzes the performance of the parallel packet switch (PPS) with a sliding window (SW) method under bursty data traffic. The PPS comprises multiple packet switches operating independently and in parallel. The typical PPS dispatch algorithm uses a round-robin method (RR) (Iyer, 2003). The class of PPS is characterized by deployment of parallel center-stage switches that all memory buffers run slower than the external line rate. A novel SW packet switching method for PPS, called SW-PPS, is proposed. Under identical bursty data traffic, the SW-PPS provided improved performance when compared to RR-PPS. A mathematical, analytical model for SW-PPS is proposed. In addition, a novel bursty data traffic model is proposed: a packet-based bursty data traffic model. This packet-based bursty data traffic model can emulate more realistic network, and thus, produces more realistic simulation results.

Input buffered switches with virtual output queues (VOQ) design to avoid head-of-line problems, is a primary design of switches that can be scalable to very high speeds. However, this design requires a complex and iterative scheduling approach and does not meet quality of service (QoS) requirements during operation. In this paper, a three-dimensional virtual output queue (3D-VOQ) switch is proposed and a scheduling algorithm under new architecture that improves the competitive transfer of service. Analysis and simulation are employed to verify the performance of 3D-VOQ, and supports high/low QoS requirements, and then improves switch performance.

In recent years much attention has been given to providing the proportional delay differentiation through the packet scheduling. The issue of the performance of the scheduling algorithms also increases in importance when the line speed increases significantly as a result of the optical technology. In this paper we propose an efficient packet scheduling scheme modified from the dynamic deficit round-robin (DDRR) scheduling algorithm. The new scheme not only provides the tuning knob for adjusting the relative QoS in the packet delay but also performs scheduling at O(1) complexity and with very small overhead. Simulation results show the effectiveness of the modified algorithm.

The paper is concerned with performance analysis of the parallel packet switch (PPS) with sliding window (SW) scheme. The PPS is composed of multiple packet switches operating independently and in parallel. The traditional PPS dispatch algorithm uses round-robin (RR) (Iyer, S., IEEE Trans. Networking, vol.11, no.2, p.314-24, 2003; Aslam, A. and Christensen, K., LCN 2002, p.270-7, 2002). The class of PPS is characterized by the deployment of parallel center-stage switches such that all memory buffers run slower than the external line rate. We propose a new SW packet switching scheme for the PPS, called SW-PPS. The SW-PPS can operate in a pipeline fashion to achieve the overall switching operation. Under Bernoulli data traffic, the SW-PPS provides significantly higher performance when compared with RR-PPS. The paper presents a mathematical analytical model for RR-PPS and SW-PPS.

As the demands on quality of service (QoS) of real-time applications over the Internet increase, many research efforts have developed various packet scheduling schemes to support differentiated services. In this paper, we propose a new multi-level packet scheduling algorithm, MLDDRR, enhanced from the existing dynamic deficit round-robin (DDRR) for the support of delay-sensitive applications. The network operator can simply change the level of service differentiation by adjusting parameters. The MLDDRR can achieve high throughput efficiently and simultaneously provide smaller delay for short packets of each service class. The feature of small delay for short packets is of great importance for improving the playback quality of real-time applications such as VoIP or scalable media stream delivery. Simulation results showing the high effectiveness and small overhead of MLDDRR are also presented.

In recent years, many research efforts focus on relative differentiated service due to the increasing requirements on quality of service for time-sensitive applications. Most of the prior research relies on time stamping arriving packets or periodically monitoring the arrival traffic to arrange the service rate or priority for each class of packets. In this paper, we propose a new efficient and robust packet scheduling scheme, called ERP-DDRR. The ERP-DDRR scheduler not only can provide proportional delay differentiation under various traffic load conditions with very small overhead but also can be implemented in terabit networks. In addition, we propose a pipelining approach to further improve the performance of the ERP-DDRR scheduler. Simulation results show that the ERP-DDRR scheduler provides excellent short-term and long-term performance. The ERP-DDRR scheduler is an excellent alternative solution for future high-speed networks.

The Internet Engineering Task Force (IETF) recommended the deployment of active queue management (AOM) in the Internet routers in 1998. There were more than 50 new AQM algorithms which have been proposed since 1999. They did not consider the server fairness problem caused by the proposed AQM mechanisms. However, it happens that one may intentionally, but in a legal way, generates many "flows" for the same job in order to grab more bandwidth. This makes bandwidth shares for other servers unfair, and makes ISP price-based services policy enforcement difficult. In this paper, we consider a novel server-based congestion control approach which is based on the well known AQM algorithm A-RED (adaptive random earlier detection) and is called SF-RED. This approach can provide fair services to different servers without affecting congestion control performance in terms of packet loss rate and queue stability. We use NS2 simulator to prove the effectiveness of our approach

This paper is concerned with a distributed, system level fault diagnosis scheme for multistage network-based multiprocessors. The target system, which we choose as a representative, employs a multistage interconnection network with 4/spl times/4 switching elements. We propose a fast diagnostic method which uses a quadtree and its coupler structure. These two quadtree structures partition the system into a number of link-independent groups. This partitioning provides an important diagnostic property; the communication paths in each link-independent group are either identical or disjoint. Several previous works in fault diagnosis investigated the multistage interconnection network only. This paper presents an entire multiprocessor diagnosis, including the detection and location of single faults caused by processor nodes, switching elements, and communication links. In addition, the diagnosis of a group of multiple faults partitioned by the tree structures is also discussed.>

This paper presents a dynamically adaptive stabilization scheme for parallel matrix computation. The scheme performs automatic error detection and correction through inserting redundant, but concurrent tracer computations within the folds of the regular computation. It also eliminates the costly row interchange used in classical pivoting. A fault-tolerant double wavefront matrix algorithmfor a MIMD array multi-processor with toroidal inter connection has been designed to demonstrate the strength of the proposed scheme. This algorithm can compute: i) matrix inverse ii) solution vector to the linear system and Hi) predetermined linear combination of the solution vector from identical algorithmic framework. This efficient tri-solution algorithm excels most other known methods in parallel performance.

The author describes efficient manipulations of general vectors on the synchronous binary n-cube structure. A general vector is defined as a set of elements stored in consecutive processors with arbitrary length and starting point, and one element per processor. New routing methods for manipulating general vectors are presented. The author focuses on six major vector manipulating functions: merge, split, rotation, reverse, compression, and expansion. They are frequently used to extract and structure data parallelism in image processing and parallel solutions of linear systems. It is observed that varying the dimension order is a key to collision-free vector manipulations. A formal network model is developed for determining when link collisions occur. With the aid of this network model dimension orders yielding collision-free routine for the six manipulating functions are identified. Collision-free routing allows data communication to complete in the optimal time-single network cycle. The dimension orders are easy to encode and decode, and they are feasible for physical implementation.>

The authors present an animation tool for visualizing the complex, dynamic behavior of parallel algorithms. The key idea behind this tool design is to abstract run-time activities and turn them into graphical representations that move and vary in location, size, and color. With proper abstractions, it establishes a technical foundation for monitoring, analyzing, and improving complex parallel algorithms. It represents animated views in an informative and coherent manner. There are two unique attributes that distinguish the animation tool from others: (1) it provides a general simulation environment for analyzing parallel algorithms with arbitrary program structures and sizes; and (2) it allows the visualization for computation status of parallel processes and their run-time interactions.>

An efficient processor allocation policy is presented for hypercube computers. The allocation policy is called free list since it maintains a list of free subcubes available in the system. An incoming request of dimension k (2/sup k/ nodes) is allocated by finding a free subcube of dimension k or by decomposing an available subcube of dimension greater than k. This free list policy uses a top-down allocation rule in contrast to the bottom-up approach used by the previous bit-map allocation algorithms. This allocation scheme is compared to the buddy, gray code (GC), and modified buddy allocation policies reported for the hypercubes. It is shown that the free list policy is optimal in a static environment, as are the other policies, and it also gives better subcube recognition ability compared to the previous schemes in a dynamic environment. The performance of this policy, in terms of parameters such as average delay, system utilization, and time complexity, is compared to the other schemes to demonstrate its effectiveness. The extension of the algorithm for parallel implementation, noncubic allocation, and inclusion/exclusion allocation is also given.>

A conflict-free routing scheme is presented for a class of parallel and distributed computing systems. The core of the scheme is a quadtree communication structure. The quadtree structure suggests a general approach to mapping a class of parallel algorithms with intensive communication requirements for selecting data from many different sources and distributing data from a single source. By properly merging messages and efficiently replicating data, the quadtree structure can complete required communications in O(log/sub 4/ M) parallel steps, where M is the network size. It is shown that the size of a quadtree communication structure can be contracted and stretched by adjusting the number of descendent nodes without affecting its conflict-free property. The relationship between the computation/communication ratio of various parallel algorithms and the number of tree levels is presented, and finally, their joint effect on the response time of combining and distributing data messages is examined. This analysis helps determine the optimal adaptation of the quadtree for minimizing the overall algorithm execution time.>

A fault-tolerant mapping scheme for a configurable multiprocessor system using multistage interconnection networks is presented. By adapting its interprocessor connections, the multiprocessor system can provide many regular topological configurations suitable for a variety of parallel computation applications. The configurability of the system is achieved by applying a set of configuration procedures to a linear address space of the system. The central idea behind the scheme is the use of two transformations to restore the linear address space in the presence of processor failures. The fault-tolerant mapping scheme is composed of three algorithms. The algorithms adaptively use the two transformations to handle three different types of faults: single faults, double faults, and triple or greater faults. It is shown that when there are a few processor failures, the algorithms can effectively achieve fault-free linear subspaces with graceful degradation.>

Presents a quadtree communication structure and two associated procedures for efficient, contention-free data searching and distribution on the BBN Butterfly parallel processor and its family. The proposed quadtree structure suggests a general approach to mapping a class of parallel algorithms with intensive communication requirements for performing two primitive operations: selecting data from many different sources and distributing data from a single source. While performing these two operations through the quadtree structure, the 'ascend' and 'descend' procedures incur no link conflicts in the Butterfly network. A concrete example of mapping the linear programming algorithm is given to show the effectiveness of the proposed quadtree communication structure.>

A resource-management mechanism is presented for a multiprocessor system consisting of a pool of homogeneous processing elements interconnected by multistage networks. The mechanism aims at making effective use of hardware resources of the multiprocessor system in support of high-performance parallel computations. It can create many physically independent subsystems simultaneously without incurring internal fragmentation,. Each subsystem can configure itself to form a desired topology for matching the structure of the parallel computation. The mechanism is distributed in nature; it is divided into three functionally disjoint procedures that can reside in different loci for handling various resource-management tasks concurrently. Simulation results show that, by eliminating internal fragmentation, the mechanism achieves better source utilization than a reference machine.>

This correspondence presents a collection of reconfiguration procedures for a multiprocessor which employs multistage interconnection networks. These procedures are used to dynamically partitipn the multiprocessor into many subsystems, and reconfigure them to form a variety commonly used topologies to match task graphs. By examining the switching capability of the interconnection network, design rules for avoiding connection conflicts are exploited. Then, on the basis of these rules, parallel procedures are designed. With the procedures, a subsystem can be reconfigured in the form of the desired topologies without interfering with other subsystems. In addition, the reconfiguration of a subsystem can be accomplished in constant time, independently of subsystem size.

This paper describes the architecture of a 2 × 2 fault-tolerant switching element which can be used to modularly construct interconnection networks for multi-processing and local computer networking. The switching element uses distributed control and circuit switching. Its good gate-to-pin ratio can facilitate VLSI implementation.