Demo Data from VLDB 2026 / reviewers in the wild / expert
Laurent Kirsch
dblp:79/8314
· DBLP profile ↗
2ranked-venue papers
0as first author
1since 2021 · last 2024
0009-0007-4121-2308ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Runtime systems and virtual machines · 50% Compilers and program optimization · 50% | |
| Artificial intelligence
1 paper |
Deep learning architectures and training · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Performance modeling and evaluation · 50% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Runtime systems and virtual machines › dynamic compilation
just-in-time compilation |
0.8 | 1 | 2024 | PyTorch 2: Faster Machine Learning Through Dynamic Python Bytecode Transformation and Graph Compilation · ASPLOS (2) 2024 |
Machine learning › Deep learning architectures and training › deep learning systems
deep learning framework |
0.2 | 1 | 2024 | PyTorch 2: Faster Machine Learning Through Dynamic Python Bytecode Transformation and Graph Compilation · ASPLOS (2) 2024 |
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation |
0.1 | 1 | 2010 | Efficient simulation of oscillatory combinational loops · DAC 2010 |
Electronic design automation › hardware verification and test
logic simulation |
0.1 | 1 | 2010 | Efficient simulation of oscillatory combinational loops · DAC 2010 |
Methods — techniques the papers use, named apart from their topics
just-in-time compilation · 1.5graph compilation · 1.5oscillation period computation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | PyTorch 2: Faster Machine Learning Through Dynamic Python Bytecode Transformation and Graph CompilationabstractThis paper introduces two extensions to the popular PyTorch machine learning framework, TorchDynamo and TorchInductor, which implement the torch.compile feature released in PyTorch 2. TorchDynamo is a Python-level just-in-time (JIT) compiler that enables graph compilation in PyTorch programs without sacrificing the flexibility of Python. It achieves this by dynamically modifying Python bytecode before execution and extracting sequences of PyTorch operations into an FX graph, which is then JIT compiled using one of many extensible backends. TorchInductor is the default compiler backend for TorchDynamo, which translates PyTorch programs into OpenAI's Triton for GPUs and C++ for CPUs. Results show that TorchDynamo is able to capture graphs more robustly than prior approaches while adding minimal overhead, and TorchInductor is able to provide a 2.27× inference and 1.41× training geometric mean speedup on an NVIDIA A100 GPU across 180+ real-world models, which outperforms six other compilers. These extensions provide a new way to apply optimizations through compilers in eager mode frameworks like PyTorch. Jason Ansel, Edward Z. Yang, Horace He, Natalia Gimelshein, Animesh Jain, Michael Voznesensky, Bin Bao, Peter Bell 0008, David Berard, Evgeni Burovski, Geeta Chauhan, Anjali Chourdia, Will Constable, Alban Desmaison, Zach DeVito, Elias Ellison, Will Feng, Jiong Gong, Michael Gschwind, Brian Hirsh, Sherlock Huang, Kshiteej Kalambarkar, Laurent Kirsch, Michael Lazos, Mario Lezcano Casado, Yanbo Liang, Jason Liang, Yinghai Lu, C. K. Luk, Bert Maher, Yunjie Pan, Christian Puhrsch, Matthias Reso, Mark Saroufim, Marcos Yukio Siraichi, Helen Suk, Shunting Zhang, Michael Suo, Phil Tillet, Xu Zhao 0004, Eikan Wang, Keren Zhou 0001, Richard Zou, Ajit Mathews, Xiaoquan Wen, Gregory Chanan, Peng Wu 0001, Soumith Chintala |
ASPLOS (2) | 23 |
| 2010 | Efficient simulation of oscillatory combinational loopsabstractThis paper presents an efficient algorithm for post-synthesis logic simulation of digital circuits with oscillatory combinational loops. Oscillatory combinational loops can significantly degrade the performance of cycle accurate logic simulators. We provide an algorithm that first, dynamically detects oscillatory loops. Then, we introduce a novel approach to compute a multiple of their oscillation period which is used to optimize the efficiency of the simulation by reducing the number of time points that need to be evaluated. Finally, we provide the experimental results of our optimized algorithm measured on a cycle accurate simulator used in conjunction with a hardware emulator. Morteza Fayyazi, Laurent Kirsch |
DAC | 2 |