A single-input and single-output (SISO) frequency-modulated continuous wave (FMCW) radar architecture is proposed and in vivo demonstrated for remote 2-D localization (range and angular information) and vital signs monitoring of multiple subjects. The radar sensor integrates two frequency scanning antennas which allow angular separation and enable determining a 2-D map (range versus angle) of a room environment from which people can be distinguished from objects and clutter. After technical tests to validate the functionality of the proposed architecture and data processing algorithm, a practical setup was successfully demonstrated to locate human volunteers, at different absolute distances and orientations, and to retrieve their respiratory and heart rate information. Experimental results show that this radar sensor can monitor accurately the vital signs of multiple subjects within typical room settings, reporting maximum mean absolute errors of 0.747 breaths-per-minute and 2.645 beats-per-minute, respectively, for respiration rate and heartbeat. Practical applications arise for Internet of Things (IoT), ambient-assisted living, healthcare, geriatric and quarantine medicine, automotive, rescue and security purposes.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

The use of in-band full duplex (IBFD) is a promising improvement over classical TDD or FDD communication schemes. To enable IBFD radios, the electrical balance duplexer (EBD) has been proposed to suppress the direct self-interference (SI) at the RF stage. The remaining SI is typically assumed to be canceled further in the digital domain. In this paper, we show that the non-zero Doppler frequencies can be extracted from the residual SI, giving information about the speed of objects in the environment. As a result, an IBFD radio can be seen as a monostatic Doppler radar which is affected by the communication signal. This paper presents a detailed performance analysis of the different sources of interference affecting the Doppler radar. The performance is also evaluated using a radar-enhanced IBFD prototype consisting of a SDR module and an EBD designed to achieve up to 55 dB Tx-Rx isolation in the 1.74 GHz RF band. A measurable Doppler component is created by moving a 15 dBsm cone at known velocities at 0. 5-1.3 m from the prototype. For an EBD SI rejection of 45 dB, speeds in the range of 200 to 800 mm/s are detected with high accuracy.

In-band full-duplex sets challenging requirements for wireless communication radios, in particular their capability to prevent receiver sensitivity degradation due to self-interference (transmit signals leaking into its own receiver). Previously published self-interference rejection designs require bulky components and/or antenna structures. This paper addresses this form-factor issue. First, compact radio transceiver feasibility bottlenecks are identified analytically, and tradeoff equations in function of link budget parameters are presented. These derivations indicate that the main bottlenecks can be resolved by increasing the isolation in analog/RF. Therefore, two design ideas are proposed, which provide attractive analog/RF-isolation and allow integration in compact radios. The first design proposal targets compact radio devices, such as small-cell base stations and tablet computers, and combines a dual-port polarized antenna with a self-tunable cancellation circuit. The second design proposal targets even more compact radio devices such as smartphones and sensor network nodes. This design builds on a tunable electrical balance isolator/duplexer in combination with a single-port miniature antenna. The electrical balance circuit can be implemented for scaled CMOS technology, facilitating low cost and dense integration.

A fully differential envelope detector (ED) operating at 2.4GHz is designed in 90nm CMOS technology. The new design uses the common-gate topology to deal with large common-mode input signals through first-order current cancellation. Thereby, a fully differential ultra-low power super-regenerative front-end is enabled. It has a measured output voltage swing of 2.8–127mV and achieves 19.6dB output SNR at sensitivity input level. The circuit consumes 3µW from a 1.2V power supply.

Analog VLSI circuits are being used successfully to implement Artificial Neural Networks (ANNs). These analog circuits exhibit nonlinear transfer function characteristics and suffer from device mismatches, degrading network performance. Because of the high cost involved with analog VLSI production, it is beneficial to predict implementation performance during design. We present an FPGA-based accelerator for the emulation of large (500+ synapses, 10k+ test samples) single-neuron ANNs implemented in analog VLSI. We used hardware time-multiplexing to scale network size and maximize hardware usage. An on-chip CPU controls the data flow through various memory systems to allow for large test sequences. We show that Block-RAM availability is the main implementation bottleneck and that a trade-off arises between emulation speed and hardware resources. However, we can emulate large amounts of synapses on an FPGA with limited resources. We have obtained a speedup of 30.5 times with respect to an optimized software implementation on a desktop computer.