While 40 years of semiconductor scaling and Moore's Law enabled system-on-a-chip (SoC) ASICs over the last decade, it is obvious that, fundamentally, both desktop and portable consumer electronics have hit the frequency and power (or thermal) wall. On the other hand, the insatiable demand of mobile computation and bandwidth, especially with the ubiquitous smartphones, has emerged and will continue to drive the technology. In this presentation, mobile computing performance explosion in host processors, multimedia co-processor engines and mobile bandwidth, as well as the opposing thermal and power limits will be addressed. As a result, even with the latest technology nodes, energy gap of a form-factor-sensitive smartphone between capability and demands continues to widen. The next wave of technology innovations from process, packaging, digital, and analog/RF circuits will be vital in solving ultra-low power challenges for the next-generation ASICs.

In the last couple of decades, handheld wireless devices such as cell phones have become one of the most prolific electronic devices in history. With this has come an exploding demand for performance and features that cover almost every aspect of our digital multimedia interconnected lives including 3-D gaming, still and video cameras, WAN, Bluetooth, high-speed data connections, and so on. As ever increasing features continue to be integrated into these products, there is an ongoing need to develop innovative ways to reduce power consumption and extend battery life. Only through continual process and circuit cooptimization are we able to reap the benefits of technology scaling required to meet the feature and performance demands in the face of increasing process variations and exponentially increasing leakage currents. As a result, SmartReflex power and performance technologies have been developed and applied to 90 nm, 65 nm, and 45 nm system-on-chip (SoC), to achieve optimal power and performance. SmartReflex technologies consist of two major components to optimize SoC power and performance: static and dynamic techniques. Static techniques like power-gating, retention and off-mode are used to lower leakage and allow for extended battery lifetimes for standby times. Dynamic techniques such as dynamic power switching, adaptive voltage scaling, dynamic voltage/frequency scaling with split-rail memories, and adaptive body-biasing address active power and performance challenges. These techniques enable SoC solutions with the performance of the latest process technology and provide the user with advanced multimedia features with orders of magnitude of power reduction.

With the latest gaming systems such as X-box, Playstation 3, PSP, IPTV, and H264 requiring more bandwidth, packaged in smaller devices, and providing higher quality, in return they evacuate more heat and consume more power, thus making power consumption and thermal dissipation a major issue for chip designers in the nanometer era.Thermal effects on the chip and package is the next wave. First, there was signal integrity. Then power integrity and now, there is a new first-order effect in the horizon for IC and system designers called thermal integrity. And the traditional design methodology of using uniform temperature across the chip is becoming woefully inadequate and provides insufficient data to the package and system designers, unable to meet the requirement and demands of the consumer. To better understand the impact of temperature variation on chip's performance, both power distribution and package characteristics must be considered in the design and analysis flow. Likewise, a realistic view of the heat distribution across the chip is becoming essential for package and system designers. What makes the analysis of signal, power, and thermal integrity effects challenging is that they must all be considered concurrently across the entire chip, which requires novel approaches to mitigate the issue.The panel will discuss how urgent is the impact of thermal integrity on system designs and is this a real concern or are we making it up?When and under what condition will it become urgent, and is it related to process nodes, low power applications, type of packaging used, etc.? Is there specific design techniques used for more specific multimedia processing? Can you separate the IC design from package and system designs with some assumptions or is co-design the only way? How accurate is the industry's understanding of the physics of the chip (device), interconnect, and package? Is thermal integrity a first order or second order effect?Given the other variations from nominal, how important is this.The moderator will conclude with a summary of the panelist comments and be able to make a forward-looking statement about the future of power and heat and their impact on system design.

Methodology, EDA Flow, scripts, and documentation plays a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on leakage reduction techniques but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are implemented to build an efficient, re-usable, robust, low cost and portable platform. Techniques have been silicon proven on the 90-nm TI CMOS technology and is commonly used to design SoC with complexities over 100 Million transistors.

This paper investigates performance, power, and energy efficiency of several CMOS master-slave D-flip-flops (DFF's). To improve performance and energy efficiency, a push-pull DFF and a push-pull isolation DFF are proposed. Among the five DFF's compared, the proposed push-pull isolation circuit is found to be the fastest with the best energy efficiency. Effects of using a double-pass-transistor logic (DPL) circuit and tri-state push-pull driver are also studied. Last, metastability characteristics of the five DFP's are also analyzed.

The paper offers a perspective of cellular standards, from first-generation (1G) and second-generation (2G), to the emerging third generation (3G). Architectures of existing 2G and future 3G systems are compared. The micro-architecture of the digital signal processor (DSP) for 2G is reviewed and requirements for 3G are summarized.

In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.

As process technology scales down to deep sub-micron and the frequency of a high-performance processor increases beyond 300 MHz, coupling induced signal integrity problems become more severe. Ignoring coupling effects can lead to functional failures or speed degradation. As a result, the traditional approach of repeater insertion driven by propagation delay and slew rate optimization becomes inadequate. The authors propose a design methodology to select optimal repeaters for high-performance processors by considering not only the delay and slew rate, but also crosstalk effects. A concurrent decision diagram (CDD) is further suggested to achieve crosstalk constraints with various trade-offs.

To optimize performance and power of a processor with both precharged and static circuit styles, a selftimed modi$ed cascade latch (MCL) is proposed for dual-rail domino to static logic interface.Compared to conventional self-timed cascade and cross-coupled NAND latches, the innovative MCL achieves the highest performance and lowest power dissipation with reasonable noise immunity.Ease of embedding logic functions in these self-timed latches is also studied.For interfacing single-rail domino to static logic, the pseudo-inverter latch (PIL) is the most power efJicient latch when compared with the conventional transparent and cross-coupled NAND latches.Based on a 0.18 p CMOS nominal-process with a 1.6 V supply voltage, effects on these latches' power dissipation and delay from scaling supply voltage and output load are presented, respectively.._.

Article Free Access Share on Hybrid dual-threshold design techniques for high-performance processors with low-power features Authors: Uming Ko Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Andrew Pua Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Anthony Hill Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile , Pranjal Srivastava Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, TexasView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 307–311https://doi.org/10.1145/263272.263362Published:01 August 1997Publication History 11citation116DownloadsMetricsTotal Citations11Total Downloads116Last 12 Months10Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

This paper investigates delay, power and area of critical components in designing energy-efficient control logic. To improve performance and energy efficiency, a split-slave dual-path (SSDP) register is proposed which improves the energy efficiency of the prior art by 30%. For multiplexers (MUX) three MUXes are proposed and compared to existing solutions. The proposed MUXes improve performance by 50% or power by 22%. The impact of scaling supply voltage alone and scaling threshold voltage with supply voltage on delay and power is also examined.

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here.>

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 /spl mu/m CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V.>