Blockchains offer a mechanism for executing code in a credible, transparent and uncensorable way. These characteristics lend themselves to the implementation of applications that guarantee different actors regarding the credible execution of mechanisms, including insurance and impartial certification. A significant challenge in this domain is enabling smart contracts to reliably access real-world state information. We propose a “cognitive” oracle architecture that makes complex and ambiguous conditions—such as identifying specific elements within an image—verifiable on-chain. Unlike traditional oracles that focus on scalar data feeds, our oracle integrates machine learning classifiers with SNARK proofs to provide trustworthy semantic evaluations. To mitigate inaccuracies and faults, the oracle also embeds a jury-based dispute resolution layer supported by verifiable machine learning explanations. We evaluate this oracle system in the context of a carbon credit application based on small-size neural network inferences. The results and cost analyses indicate that the economic viability of such an oracle depends on minimizing dispute frequencies and selecting optimal configurations. The inclusion of explanation methods adds a layer of game-theoretic complexity but also enhances the quality of the jury’s work, as well as overall transparency and trust.

Federated Learning (FL) is an advancement in Machine Learning motivated by the need to preserve the privacy of the data used to train models. While it effectively addresses this issue, the multi-participant paradigm on which it is based introduces several challenges. Among these are the risks that participating entities may behave dishonestly and fail to perform their tasks correctly. This misbehavior, in turn, also threatens privacy, because an undetected deviation in training or aggregation can silently undermine the confidentiality guarantees that FL was designed to provide. This motivates mechanisms that provide checkable evidence that released checkpoints are consistent with a declared learning specification and an auditable execution trace. In this SoK, we model federated learning as an append-only transcript of submissions, admissions, aggregation, and finalization events, and formalize verifiability as a collection of integrity claims issued by clients and the aggregator, and checked by different verifier classes. We derive a taxonomy of recurring client-side and aggregator-side claims and use it to analyze representative verifiable FL (VFL) systems spanning Zero-Knowledge Proofs (ZKP) and Trusted Execution Environment (TEE) technologies. Our analysis suggests that, while verifiable aggregation is comparatively mature, data verifiability appears feasible but still sparsely adopted in practice, and verifiable training remain costly and rarely scale to modern models.

Blockchain technology has the potential to transform the gaming industry by enabling players to own in-game assets and receive NFTs or tokens as rewards for their accomplishments. However, one critical issue is determining how to ensure that achievement conditions are met (e.g., that the player completed level number 10). Current approaches either open cheating backdoors (e.g., if the client checks the conditions) or introduce centralization points and limitations (if a backend checks the condition). To overcome these problems a potential solution may seem to execute games directly on-chain, but the high computational cost (especially on Ethereum) and latency has made it impossible so far; however, the development of new technologies like proofs of computation enables new approaches. In this article we employ succinct proofs of computation to allow the player to prove to a smart contract on a blockchain that he reached (achieved) a certain state in an action game, that can then be played directly in the client; this allows to implement decentralized systems that can ensure fair and transparent rewarding. Moreover, we address the problem of proving that a certain game on the client has taken no more than a specific amount of time.

As digital identity gains increasing importance, current centralized digital identity systems face significant limitations. Recent years have seen a shift towards decentralized and self-sovereign identity models, underpinned by verifiable credentials and cryptographic signatures. A critical challenge in these systems is credential revocation, presenting unique issues absent in centralized systems. In this context, blockchain (BC) systems offer a viable support for implementing revocation mechanisms without compromising the advantages of decentralized identity. However, they introduce storage and cost challenges. This work proposes a credential revocation approach utilizing a Merkle tree-based accumulator. Our accumulator enables a trade-off between anonymity and proof complexity, offers resistance to credential tracking, and relies solely on hash function collision resistance, making it quantum-safe. Additionally, we have integrated the accumulator within a broader identity management library and reported its performance on standard hardware.

Tokens are digital, transferable, and programmable assets and one of the most promising tools offered by blockchains. They could enable a wide range of applications, from down to earth to futuristic. One of the main issues in achieving wide adoption of tokens is onboarding: main platforms require users to deal with specific tools such as wallets, transaction fees, key generation, and storage. The most common solution to offer a familiar experience to naive users are custodial intermediaries, which have the important drawback of centralizing the process, and keeping users away from the advantages of self-sovereign assets control. In this paper, we present a process for the distribution of digital tokens to end users, exploiting “physical” objects for initial distribution. The process is aimed at making the onboarding of users not yet accustomed to blockchain tools and concepts as easy as possible, in a secure and decentralized way.

If on one hand the possibility of using pseudonymous identities is an important feature of blockchains and smart contracts, on the other hand official identity can be required in some applications to comply with regulations such as Know Your Customer and Anti Money Laundering. These regulatory compliance issues are usually dealt with either through “custo-dial” approaches, which however neutralize the decentralization of these systems, or with “whitelisting” mechanisms, that present critical issues with regard to privacy. In this paper we propose a protocol that allows only potentially identifiable users to use a given decentralized applications. The system ensures that users are identifiable only by a competent authority, under certain conditions, and that in any other case they remain pseudonyms. To evaluate performance and costs, we present an Ethereum implementation of the protocol.

Tokens are digital, transferable and programmable assets and one of the most promising tools offered by blockchains. They could enable a wide range of applications, from down to earth to futuristic. One of the main issues in achieving wide adoption of tokens is onboarding: main platforms require users to deal with specific tools such as wallets, transaction fees, key generation and storage.The most common solution to offer a familiar experience to naive users are custodial intermediaries, which have the important drawback of centralizing the process, and keeping users away from the intrinsic advantages of blockchains.In this paper we present a process for the distribution of digital tokens to end users, exploiting "physical" objects for initial distribution. The process is aimed at making onboarding of users not yet accustomed with blockchain tools and concepts maximally easy, in a secure and decentralized way.

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task. In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, subportions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually optimized solutions, and orders of magnitude higher than those generated by commercial high-level synthesis tools.

This work proposes a reconfigurable system able to perform - through a parallel and pipelined core, called ReCPU - regular expression matching. The system can configure on the programmable device, such as a FPGA, a set of ReCPUs, each one exploiting a single instance of the regular expression matching task on the given input string. These cores work in parallel on the same string analyzing different possible matching of the regular expression. Since the system is able to exploit dynamic partial reconfigurations, it can adapt at run-time the number of cores configured on the device, accordingly with the complexity of the regular expression. The adoption of the proposed solution makes it also possible to parallelize the regular expression matching process with a multiple cores architecture drastically reducing the time required for the completion of the task. Finally, run-time reconfiguration capabilities also allow to reduce the amount of resources required by the proposed approach.

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

The use of Field Programmable Gate Array (FPGA) based System on Chip (SoC) is a promising approach in Multimedia applications. In SoC, computationally intensive tasks are off-loaded to the hardware logic. A feature introduced with new FPGA devices, Dynamic Partial Reconfiguration (DPR) is suitable to change this hardware logic when needed and while the rest of the system continues its functioning. As the applications running on hardware logic are real-time and computationally intensive, in order to make use of DPR to change the hardware logic, the efficiency of the DPR process is crucial. This paper describes how a FPGA-based Multimedia Application (Audio-Video filtering), benefits from dynamic partial reconfiguration and a custom DPR controller: the Speed Efficient Dynamic Partial Reconfiguration Controller (SEDPRC). Experimental results have shown that the novel controller brings benefits to the reconfiguration time. Enhancements in reconfiguration throughput up to a 55× factor are achieved.

This paper presents a ripple-carry adder module that can serve as a basic component for Quantum Dot Automata arithmetic circuits. The main methodological design innovation over existing state of the art solutions was the adoption of so called minority gates in addition to the more traditional majority voters. Exploiting this widened basic block set, we obtained a more compact, and thus less expensive circuit. Moreover, the layout was designed in order to comply with the rules for robustness again noise paths [6].

We present a reconfigurable architecture that can perform highly parallel regular expression matching. The system can be configured on programmable devices such as FPGAs as a set of instances of a predefined core called REMA. Each core addresses one of the subtasks into which the regular expression matching problem can be partitioned. These cores work in parallel on the same string analyzing different possible matchings. Since the system can exploit dynamic partial reconfigurations, it can adapt the number of cores configured on the device at run-time, according to the complexity of the regular expression, which is proportional to the number of different ways in which the reference string can be mapped on pattern. Making it possible to parallelize the matching process with a multiple core architecture drastically improves temporal efficiency (up to one order of magnitude with respect to software solutions and up to a speedup factor of 25 with respect to hardware solutions). Most important, the run-time reconfigurability feature allows to implement a just in time logic usage strategy, thus reducing the mean amount of resources required.

In this paper, we address the problem of P-equivalence Boolean matching. We outline a formal framework that unifies some of the spectral- and canonical-form-based approaches to the problem. As a first major contribution, we show how these approaches are particular cases of a single generic algorithm, parametric with respect to a given linear transformation of the input function. As a second major contribution, we identify a linear transformation that can be used to significantly speed up Boolean matching with respect to the state of the art. Experimental results show that, on average, over a large set of randomly generated Boolean functions, our approach is up to five times faster than the main competitor on 20-variable input and scales better, allowing to match even larger components. Finally, as a representative set of Boolean functions that arise in practice, we considered multiplexers with three, four, and five selectors and functions extracted from the ISCAS85 benchmarks suite with a number of input variables up to 20. The reported performance results show that our approach allows us to halve the canonizing computation time.

Dynamic reconfiguration capabilities of FPGA devices are commonly exploited in order to perform changes in a system with respect to computational elements. In this paper, we propose a framework able to exploit different levels of simulations in order to perform a requirements-driven design of the communication infrastructure of a reconfigurable system, so that the overall performances can be improved. To accomplish this requirements-driven design it is necessary to perform a design space exploration of applications and scenarios in which a particular system can be used. A new scenario-centric approach is proposed in order to identify metrics and requirements needed to apply a communication infrastructure reconfiguration.

We propose a methodology for the early estimation of communication implementation choice effects, starting from an abstract transaction-level system model (TLM). The reference version of the TLM considered is the Open SystemC initiative library. The methodology is based on the computation of metrics that abstract useful information from the initial system model. The metrics are precisely defined upon a general formal model of transaction-level system descriptions. A set of design problems of relevant interest, such as shared communication resource assignment, pipelining partitioning, bandwidth, and latency constraint estimation, is considered to show some potential applications of the metrics proposed.

In this paper, we face the problem of P-equivalence Boolean matching. We outline a formal framework that unifies some of the canonical form-based approaches to the problem.

In this paper, we present new canonical forms for P, NP and NPN equivalence relations on boolean functions. The canonical forms are based on the minimization of a cost function. With respect to previous approaches based on cost minimization, our function allows the minimization algorithm to explore a reduced solution space. This reduction is obtained by partitioning the columns of the boolean function through an equivalence relation. NP and NPN canonical forms are obtained by means of a preprocessing step of negligible computational overhead.

In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In particular, the issues related to the synthesis of the communication between the system elements are considered. The context in which the analysis is performed is the design flow proposed in the ODETTE project: in this ambient, systemC is exploited in order to provide efficient system-level models; after that, the systemC+ systemC subset and extensions can be used to get a refined description that, despite the use of object oriented features such as polymorphism and inheritance, can be automatically synthesised by means of the ODETTE tools. Still, the problem of interfacing the hardware synthesised with the other elements of the design (memories, peripherals) remains an important issue. In order to face this problem, we propose a pattern that can be used to design bus interfaces that allow both an high level of abstraction in the communication on the "user" side, and automatic synthesis by the ODETTE tools. In order to do this, OSSS global objects are exploited to implement the communication between the application and the interface. After presenting the general methodology, a specific library interface is presented, that could connect the device under design to a PCI bus. In order to prove the viability of the approach, an example of synthesis of an example, from the system level down to the RT level is performed.

The introduction of design languages, such as SystemC 2.0, that allow the modelling of digital systems at the transaction level will impose some major changes to the design flows. Since these formalisms allow for a higher level of abstraction in the systems description, new methodological tools will be needed to support all design phases. The goal of this paper is twofold: first we formalize in an abstract way a significant set of features of a Transaction Level Model, according to the SystemC 2.0 formalism. Then, upon this model we define numerical metrics that can provide useful information in the analysis of the system-level specifications. In particular these metrics are useful in the design exploration phase, to define the main characteristics of the hardware and software architectures

Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update and enrich HW design methodologies to face abstraction and novel requirements. Here we present some results of design practice of HW modules in this context. Co-simulation and synthesis are combined in this approach to achieve higher abstraction levels in the design, to improve validation and re-use of previous designs and human experience. The proposed methodology is embedded in a SystemC based design flow. The SystemC-VHDL co-simulator tool is also based on a SystemC/C++ front-end developed to support the co-simulation between VHDL and SystemC. The prototypal state of the adopted tools increase the novelty and interest of the approach.

In this paper, we present the results of a set of experiments we conducted in order to evaluate the viability of behavioral synthesis, relying on the tools available at the moment in the EDA market. To accomplish this we modelled a complex PCI bus interface in SystemC using a behavioral style of description. Then we tried to synthesize it by means of the Synopsis CoCentric SystemC compiler tool. The problems arisen during synthesis, in particular those concerned with the cycle-accurate timing behavior of the synthesized circuit, were addressed. After analyzing them, possible solutions were proposed, where possible. Finally, a summary of the pros and cons of the behavioral synthesis in SystemC is presented.

Summary form only given. The combined effects of devices increased complexity and reduced design cycle time creates a testing problem: an increasing larger portion of the design time is devoted to testing and verification. Today EDA tools, moving towards higher levels of abstraction, promise greater designer productivity, resulting in increased design complexity and size. In order to reduce the testing and verification time, different high-level approaches have been proposed in literature. Most of these approaches are based on the definition of an error or fault model, applicable at a higher level of abstraction of the description of the system to be implemented. In this paper we concentrate our attention on the evaluation of error models, used in test generation and in functional verification. Evaluation of error models is also an important aspect when fault injection methodologies are used to evaluate the dependability of complex system.