Summary form only given. It is pointed out that, with the advent of ultra-large-scale integration, the design and test of digital circuits are becoming more and more difficult. Effective approaches to solving this problem are hierarchical processing and structured design-for-testability. It is noted that design verification and automatic test generation systems can handle a circuit with millions of gates by using a hierarchical processing approach and a partitioning technique based on scan-path structure.>

A hierarchical timing verification system is described. It can evaluate all logical paths in a chip without any specific manual input information, using a path tracing algorithm.

A mixed level simulator, MIXS, is a logic verification tool which has multiple simulation capabilities. Main MIXS techniques are time wheel and selective trace algorithm for functional level simulation based on 'node' model concept and the linkage function of functional models, described in different detail, with network information. The mixed level simulation for large digital systems can be achieved very efficiently by using the above techniques.