This paper presents the first experimental demonstration of fully Walsh-based wideband converters for Radio Frequency Front-End (RFFE) architecture implemented in 28 nm FDSOI CMOS technology. The system integrates a Walsh-based RF digital-to-analog converter (WDAC) and a Walsh-based RF analog-to-digital converter (WADC) designed for digital predistortion (DPD) applications. The WDAC achieves an instantaneous bandwidth of 4.7 GHz with an energy efficiency of 0.57 pJ/bit. The WADC achieves a 2.5 GHz bandwidth while consuming only 4 mW. The experimental demonstration showcase efficient wideband signal processing in the Walsh domain and highlights its potential as a promising paradigm for future low-power, high-throughput wireless transceivers, offering both wideband capabilities and a new order of scale energy efficiency.

This work details a new way to deal with the Multiple-Cell Upsets (MCU) in SRAM memories for space applications. The method consists of spatially interleaving a memory plan with a network of memory radiation detectors. As a proof-of-concept, a prototype circuit composed of the radiation detectors was manufactured in the 350 nm CMOS Process Technology and tested considering two methodologies: electrically-induced SEU/MCU testing and SEE laser testing. Silicon measurement results confirm the correct operation of the circuit, detecting single and multiple events inserted in different positions of the evaluated detection plans. According to the ratio between the number of data and detection cells, the method proposed can provide a probability of detecting MCUs in a memory plan that can reach close to 100%.

A novel non-linear adaptive filter for the linearization of Radio Frequency (RF) Power Amplifiers (PAs) is presented. In this study, we aim at reducing the Digital Predistortion (DPD) complexity and enhancing its convergence speed for reduced computation time. The Walsh Transform is used as a computational basis for evaluating a predistorter (PD) model. The mathematical properties of the Walsh theory are exploited to adapt a memory polynomial (MP) in the sequency domain. A block-based Walsh LMS is introduced to seek the optimal PD coefficients. Simulations and results of linearization of class-AB PAs are exhibited. The comparison with conventional DPD algorithms shows that the proposed method converges 10 times faster with a reduction of 12% of the complexity for similar accuracy. Finally, a complete DPD architecture based on the Walsh Transform is proposed.

This paper presents a very low-power 875 MS/s 7b single-channel high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a SNDR/SFDR at Nyquist rate of 41.46/55.01 dB. The use of an integer-based split CDAC combined with an improvement for the LSB capacitor allows a substantial improvement in the SNDR. A simple and accurate calibration procedure for the ADC is presented thanks to body biasing. The ADC is designed in 22 nm FDSOI while consuming 1.65 mW from a 0.8 V supply with a core chip area of 0.00074 mm2. The Walden figure-of-merit of 19.5 fJ/conversion-step at Nyquist rate making it one of the lowest among recently published medium resolution SAR ADCs.

In order to implement a built-in self-test (BIST) strategy for a radio frequency (RF) LC-voltage controlled oscillator (VCO) devoted to WiMax applications, an exhaustive study of the fault coverage achievable for this block is carried out. The peak-to-peak value of the output voltage is shown to be the best quantity to monitor. Once the fault is detected, it is shown that the BIST can be exploited as well to trigger a feedback allowing, in some cases, the self-correction of the VCO. The complete system is designed using the STM CMOS 65 nm process.

An otherwise well-known ratiometric built-in current sensor (BICS) dedicated to monitor the current of analog and mixed-signal building blocks highlights a dependency with regards to technology discrepancy. In this paper we present a design methodology that allows to dramatically reduce the dependency, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the BICS proposed has a peak-to-peak dispersion lower than 10 % of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self test methodology is illustrated by monitoring the supply current of a low-noise amplifier (LNA). Measurements confirm the BICS's low sensitivity to process variations and its transparency relative to the circuit under test (CUT)