The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm 2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.

EuroHPC Joint Undertaking is a new European Union's strategic entity focused on pooling of the Union's and national resources on HPC to acquire, build and deploy the most powerful supercomputers in the world within Europe. This talk explores the European Processor Initiative (EPI), one of the cornerstones of this European strategic plan, a joint collaboration between more than twenty partners, representing industrial companies, academia and research centres with the goal to build a production processor with drastically better performance and power in support of the EU's focus on delivering its own Exascale-systems built on EU IP and achieving processor independence. Launched in December, the first three years draws processor and platform design; embedded software, middleware, applications and usage experts from 10 EU countries together to co-design Europe's first HPC Systems on Chip and accelerator technologies. The EU-CPU family is targeted to debut in 2020 on a pre-exascale prototype system and production-ready by the 2021 timeframe.

Bio-medical image processing in the field of telemedicine, and in particular the definition of systems that allow medical diagnostics in a collaborative and distributed way is experiencing an undeniable growth. Due to the high quality of bio-medical videos and the subsequent large volumes of data generated, to enable medical diagnosis on-the-go it is imperative to efficiently transcode and stream the stored videos on real time, without quality loss. However, online video transcoding is a high-demanding computationally-intensive task and its efficient management in Multiprocessor Systems-on-Chip (MPSoCs) poses an important challenge. In this work, we propose an efficient motion- and texture-aware frame-level parallelization approach to enable online medical imaging transcoding on MPSoCs for next generation video encoders. By exploiting the unique characteristics of bio-medical videos and the medical procedure that enable diagnosis, we split frames into tiles based on their motion and texture, deciding the most adequate level of parallelization. Then, we employ the available encoding parameters to satisfy the required video quality and compression. Moreover, we propose a new fast motion search algorithm for bio-medical videos that allows to drastically reduce the computational complexity of the encoder, thus achieving the frame rates required for online transcoding. Finally, we heuristically allocate the threads to the most appropriate available resources and set the operating frequency of each one. We evaluate our work on an enterprise multicore server achieving online medical imaging with 1.6x higher throughput and 44% less power consumption when compared to the state-of-the-art techniques.

The Horizon 2020 MANGO project aims at exploring deeply heterogeneous accelerators for use in High-Performance Computing systems running multiple applications with different Quality of Service (QoS) levels. The main goal of the project is to exploit customization to adapt computing resources to reach the desired QoS. For this purpose, it explores different but interrelated mechanisms across the architecture and system software. In particular, in this paper we focus on the runtime resource management, the thermal management, and support provided for parallel programming, as well as introducing three applications on which the project foreground will be validated.

Provided unified learning platform, which is developed as a main goal of our ICT FP7 - Collaborative Project: Embedded Computer Engineering Learning Platform enables modular approach in education of computer engineers. It helps engineering education personnel to transform passive listener's students into active learners, thus stimulating students to actively participate in the learning process. Furthermore, this platform shall introduce a flexible and extendable learning environment for upcoming technologies in embedded systems, thus providing a long lasting educational solution for academia. This work in progress article describes capabilities of our learning platform.

To overcome a complex and multidisciplinary approach which includes understanding of various systems based on different technologies and system solution optimizations in engineering education for embedded systems at university level and provide a complex and multidisciplinary approach, the first cycle of the design of a unified, multiple-target platform that will enable integrated approach to computer engineering and embedded systems learning has been finished so far. This work shows results of current research, preliminary conclusions and future focuses.

IDEA is a symmetric block cipher with a 128-bit key proposed to replace DES where a strong encryption is required. Many applications need speed of a hardware encryption implementation while trying to preserve flexibility and low cost of a software implementation. In this paper we have presented one solution of this problem. Our system architecture uses a single core module named Round to implement the IDEA algorithm. Using the core we were able to implement and test an example application in only three days. This "off the shelf" solution for designing a cryptographic application using the IDEA algorithm significantly reduced the design cycle, thus greatly reducing time-to-marker and cost of such designs. By increasing the number of the Round modules, a system designer can linearly increase the speed of the design. This system design methodology makes it possible to achieve the necessary performance, or to preserve area (and reduce costs) when needed unlike other known approaches. We have implemented one Round UNICORN architecture in Xilinx FPGA. After implementation the chip has been tested using the standard test vectors and it was capable of performing 2.8 Mbps encryption in both ECB and CBC mode.

In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard. The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024/spl times/1024 color images.>

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2- mu m CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second.>