Summary form only given. The effect of Intel/spl reg/ hyper-threading (HT) technology on a system's performance varies according to the characteristics of the application running on the system and the configuration of the system. High performance computing (HPC) clusters introduce additional variables, such as the math libraries used in solving linear algebra equations that can affect the performance of scientific and engineering applications in particular. We study the effect of HT on MPI-based applications by varying the math library. We configure an Intel-based HPC cluster and used the High Performance Linpack (HPL) benchmark to study the performance characteristics without changing hardware or communication parameters, but by linking the application with different math libraries. What we have found is that, even though the application or hardware parameters remain the same, HT may help or hinder the overall performance of the cluster depending on the computational efficiency of the mathematical functions.

This paper presents a performance study of two commodity clusters built from two models of Dell PowerEdge servers. Both clusters have eight servers interconnected by GigaNet for fast message passing and by Fast Ethernet for Network File System (NFS) traffic. The two server models are different in processors, level 2 (L2) cache, speed of front-side bus (FSB), chipsets and memory subsystem. They represent generic servers from two generations of Intel-based architecture. In this study, we use well-known benchmark programs to understand how they perform for computation-intensive applications. We first study their performance in stand-alone environment to unveil the performance characteristic of a compute node. We further explore their aggregated performance when they are used in a cluster environment. We are particularly interested in their scalability, per-processor performance degradation due to memory contention and inter-process communications and the correlation between results from different benchmark programs. We found that L2 cache and memory subsystem have significant impact on computation-intensive parallel applications such as the NAS Parallel Benchmark (NPB) programs. For configurations with a large number of processors (or multiple processors per compute node), some of NPB programs perform better on platform with larger global L2 cache, even though the platform has slower processors, FSB and memory components.

GigaNet and Myrinet are two of the leading interconnects for clusters of commodity computer systems. Both provide memory-protected user-level network interface access, and deliver low-latency and high-bandwidth communication to applications. GigaNet is a connection-oriented interconnect based on a hardware implementation of Virtual Interface (VI) Architecture and Asynchronous Transfer Mode (ATM) technologies. Myrinet is a connection-less interconnect which leverages packet switching technologies from experimental Massively Parallel Processors (MPP) networks. This paper investigates their architectural differences and evaluates their performance on two commodity clusters based on two generations of Symmetric Multiple Processors (SMP) servers. The performance measurements reported here suggest that the implementation of Message Passing Interface (MPI) significantly affects the cluster performance. Although MPICH-GM over Myrinet demonstrates lower latency with small messages, the polling-driven implementation of MPICH-GM often leads to tight synchronization between communication processes and higher CPU overhead.