A concentrator is an interconnection network with n inputs and m outputs, n > m, wherein any specified subset of inputs of size less than or equal to some number, called the network's actual capacity, can always be simultaneously connected to some equal-sized but unspecifiable subset of outputs. Guaranteed throughput as described by actual capacity has heretofore been the principle measure for evaluating concentrator performance. In many applications, however, a more practical measure of a concentrator's capability is a probabilistic measure of its throughput in the following sense: given an input subset of size k, k ≤ m, what is the average number of inputs that can be connected to outputs? This measure will be called expected capacity. This paper considers the expected capacity of a special class of sparse crossbar concentrators called ( m 2 ) networks. It is seen that the expected capacity values for ( m 2 ) networks are usually quite close to k.

In a memory using shuffle interconnections, the concept of sequential accessing in unit time has been related to the existence of a sequence of operations, called a tour, that moves each datum through the read/write port. For memories of size 32, it has been stated that for certain operations no tours exist at window 1; moreover, the existence and construction of tours at other windows and for larger memories have been left as open questions. In this paper, we present several processes for random and sequential accessing, together with their mathematical properties. Furthermore, we give the complete tour structure for all memories of size 2r, 2 ≤ r ≤ 6. Finally, we show how to obtain tours on a memory of size 256 from tours on a memory of size 16.