This paper compares different DeltaSigma modulation techniques for direct digital frequency synthesis (DDS). DeltaSigma modulators such as MASH, feedforward, feedback, and error feedback have been implemented in both the phase and frequency domains in a CMOS DDS prototype IC fabricated in a 0.35-mum CMOS technology with core area of 1.7times2.1 mm2and total current consumption of 75 mA. Measured DDS performance demonstrates that the frequency domain DeltaSigma modulation technique achieves better output spectrum purity than the phase domain method. Moreover, a programmable feedforward DeltaSigma modulator is proposed to achieve different in-band and out-band noise shaping effects for DDS applications.

A DC-offset cancellation scheme in the 5 GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of 13 dB at 5.2 GHz, noise figure of 9.67 dB, IIP3 of 7.6dBm. The solution provides 39.1 dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9 dB, the added power dissipation is 0.1 mW and was fabricated in 60 GHz 0.35 mum SiGe BiCMOS technology

This paper present a 100MHz 12-bit digital to analog converter (DAC) capable to work under ultra-wide temperature (UWT) range from -180degC to +120degC and at ultra low temperature (ULT) of -230degC. To obtain high resolution and good speed over the UWT, partial thermometer-decoded and segmented scheme is employed. A bandgap voltage reference is designed for UWT applications. The cryogenic DAC chip is implemented in a 0.5mum SiGe technology with die area of 4.08times2.34 mm2and total power consumption of 105mW with a 3.3V supply voltage

A new numerical method for automated design of MOSFET impurity profiles is presented. For a discrete mesh, the method efficiently calculates the gradient of electrostatic potential at each point in the semiconductor with respect to changes in the impurity concentration at every other point in the semiconductor. The gradient information is then used to adjust the profile to achieve a desired conduction condition in the device. Profile templates may be used to control the shape of profiles used during the design of enhancement- and depletion-mode threshold voltages. Profiles may also be designed to give a specified depletion-mode MOSFET conduction level or can be optimized for minimum substrate sensitivity or temperature dependence.

A new, computationally efficient method for the numerical evaluation of the equilibrium capacitance of one-dimensional MOS structures is presented. Capacitance-voltage (C-V) characteristics for arbitary impurity profiles and interface state distributions can be calculated for temperatures ranging from 50 K to 350 K. Examples of simulated C-V characteristics demonstrate the capability of the computer program MOSCAP using these techniques.