This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2|n| runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings.

This paper presents a run-length-based compression method considering dimensions of pattern information. Information such as pattern length and number of pattern runs is encoded to denote the compression status. The decoder is simple and requires very low hardware overhead. Significant improvements are experimentally demonstrated on larger ISCAS'89 benchmarks.

Large test data volume and excessive testing power are two strict challenges for VLSI testing. This paper presents a deterministic BIST using multiple LFSRs to generate the low power test set. Experimental results show, the two problems, especially in the reduction of testing power, can be significantly improved with limited hardware overhead.

We propose a fuzzy-based approach which provides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus be determined to reflect a change of circuit properties.

Partitioning a digital circuit into modules before implementing it on a single chip is key to balancing between the test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistical analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible, since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.

In this paper, we present a novel and efficient approach to test MCM at the module as well as chip levels. Our design incorporates the concept of the multifrequency test method and the smart substrate to provide two levels at speed test. The IEEE 1149.1 boundary scan standard is used to offer the necessity of controllability and observability. Part of the boundary scan cells used in the chip level are modified to form the module level scan chain. Using the chip level boundary scan cells to provide both chip and module level testings, it not only decreases area overhead but also reduces extra delay introduced by the addition of test circuits. The contribution of this paper is to provide an MCM design for testability strategy which has the capability to detect performance defects as well as static faults with small delay and low overhead.