VLDB 2026 Research / reviewers in the wild / expert
David W. Oehmke
dblp:80/5792
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2005
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture
multithreading |
0.1 | 1 | 2005 | How to Fake 1000 Registers · MICRO 2005 |
Processor architecture and microarchitecture › register file
register file design |
0.1 | 1 | 2005 | How to Fake 1000 Registers · MICRO 2005 |
Processor architecture and microarchitecture › register file
register window |
0.1 | 1 | 2005 | How to Fake 1000 Registers · MICRO 2005 |
Methods — techniques the papers use, named apart from their topics
cycle-accurate simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2005 | Intrinsic Checkpointing: A Methodology for Decreasing Simulation Time Through Binary ModificationabstractWith the proliferation of benchmarks available today, benchmarking new designs can significantly impact overall development time. In order to fully test and represent a typical workload, a large number of benchmarks must be run, and while current techniques such as SimPoint and SMARTS have had considerable success reducing simulation time, there are still areas of improvement. This paper details a methodology that continues to decrease this simulation time by analyzing and augmenting benchmark binaries to contain intrinsic checkpoints that allow for the rapid execution of important portions of code thereby removing the need for explicit checkpointing support. In addition, these modified binaries have increased portability across multiple simulation environments and the ability to be run in a highly parallel fashion. Average speedups for SPEC2000 of roughly 60x are seen over a standard SimPoint interval of 100 million instructions corresponding to a reduction in simulation time from 3.13 hours down to 3 minutes Jeff Ringenberg, Chris Pelosi, David W. Oehmke, Trevor N. Mudge |
ISPASS | 3 |
| 2005 | How to Fake 1000 RegistersabstractLarge numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading). Support for both of these together requires a multiplicative number of registers that quickly becomes prohibitive. We overcome this limitation with the virtual context architecture (VCA), a new register-file architecture that virtualizes logical register contexts. VCA works by treating the physical registers as a cache of a much larger memory-mapped logical register space. Complete contexts, whether activation records or threads, are no longer required to reside in their entirety in the physical register file. A VCA implementation of register windows on a single-threaded machine reduces data cache accesses by 20%, providing the same performance as a conventional machine while requiring one fewer cache port. Using VCA to support multithreading enables a four-thread machine to use half as many physical registers without a significant performance loss. VCA naturally extends to support both multithreading and register windows, providing higher performance with significantly fewer registers than a conventional machine David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt |
MICRO | 1 |