Thanks to the immunity against Single Event Upsets in configuration memory, Flash-based FPGA is becoming widely adopted in mission- and safety-critical applications, such as in aerospace field. However, the decreasing of device feature size leads to an increasing of the device sensitivity regarding Single Event Transients (SETs). In this paper, we developed a new workflow to evaluate SET phenomena in a specific convergence case and introduce a new mitigation of SET pulse without introducing any performance penalization to the original netlist.

General Purpose Graphical Processing Units (GPGPUs) are increasingly used in safety critical applications such as the automotive ones. Hence, techniques are required to test them during the operational phase with respect to possible permanent faults arising when the device is already deployed in the field. Functional tests adopting Software-based Self-test (SBST) are an effective solution since they provide benefits in terms of intrusiveness, flexibility and test duration. While the development of the functional test code addressing the several computational cores composing a GPGPU can be done resorting to known methods developed for CPUs, for other modules which are typical of a GPGPU we still miss effective solutions. This paper focuses on one of the most relevant module consists on the scheduler core which is in charge of managing different scalar computational cores and the different executed threads. At first, we propose a method for evaluating the fault coverage that can be achieved using an application program. Then, we provide some guidelines for improving the achieved fault coverage. Experimental results are provided on an open-source VHDL model of a GPGPU.

Due to the decreasing feature sizes of VLSI circuits, radiation induced Single Event Transients (SETs) are increasingly dominating the event ratio on modern VLSI devices. In particular, Flash-based FPGAs are characterized by the main concern of radiation-induced voltage glitches or SETs in the combinational logic. Transient pulses can be sampled by a storage element and can propagate through the circuit up to the outputs and leading to an error. In this paper, we propose a complete implementation flow including sensitivity analysis, fault tolerant mapping and fault tolerance-oriented place and route for the effective design of SET tolerant circuits on Flash-based FPGAs. In details, the proposed method allows accurate measurement of the transient pulse source induced by radiation particles and estimation of the SET error rate on the overall circuit. Besides the developed method provides a netlist mapping and place and route tool for the selective mitigation of SET effects. The proposed method has been applied to an industrial design oriented to the Euclid European Space Agency mission including more than ten different modules. The obtained results show an improvement of the total filtering capability of around 43 times with respect to the original netlist without affecting the timing constraints of the circuit.

Due to technology scaling, which means smaller transistor, lower voltage and more aggressive clock frequency, VLSI devices are becoming more susceptible against soft errors. Especially for those devices deployed in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g. aging and wear-out effects) also have negative impacts on reliability of modern circuits. Furthermore, as recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems, for avionic and space applications, certain fault tolerant strategy must be applied to guarantee system reliability throughout application lifetime. In this paper, we focus on two aspects: testing for System-on-Chip/System-on-Programmable-Chip by exploiting debug infrastructures and analysis and mitigation of Single Event Effects on FPGA devices.

When facing in-field board test, the functional approach plays an important role. Often, it corresponds to forcing the processor to execute a test program (which could be an application one), observing the produced results (e.g., by looking at the results written in the memory at the end of the test program execution). However, the fault coverage that can be achieved in this way is often difficult to compute, and limited by the reduced observability. In this paper we propose to use the debug features provided by many processors to enhance the observability, and hence the achieved fault coverage. In the proposed architecture we monitor on-the-fly during the test program execution the information accessible through the debug port using an ad hoc module mapped on an FPGA which is assumed to exist close to the processor. We provide experimental results showing the feasibility and cost of the approach, and demonstrate that it can provide a significant increase in the achieved fault coverage with respect to the popular solution of observing the final content of the memory.

This work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial tool-chain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average.

The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.

Over the past decade, the complexity of electronic devices in the automotive systems increased significantly. The modern high level vehicles include more than 70 Electronic Control Units (ECUs) aimed at managing the powertrain of the vehicle, and improving passengers' comfort and safety. ECU microcontrollers aimed at the control of the fuel injection system have a key role. In this paper we present a new FPGA-based platform able to supervise and validate Commercial-Off-The-Shelf timer modules used in today state-of-the-art software applications for automotive fuel injection system with an accuracy improvement of more than 20% with respect to traditional approach. The proposed approach allows an effective and accurate validation of timing signals and it has two main advantages: can be customized with the exact timing module configurations to meet the exigency of new tests and allows effective modularity design test. As case study two industrial Time Modules manufactured by Freescale and Bosch have been used. The experimental analysis demonstrates the capability of the proposed approach providing a timing and angular precision of 10 ns and 10−5degrees respectively.

Detecting the effects of transient faults is a key point in many processor-based safety-critical applications. This paper proposes to adopt the debug interface module existing today in several processors/controllers available on the market. In this way, we can achieve a good detection capability and small latency with respect to control flow errors, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches and we experimentally evaluated its characteristics demonstrating the advantages and showing the limitations on two pipelined processors. Experimental results performed by fault injection using different software applications demonstrate that the method is able to archieve high fault coverage (more than 95 percent in nearly all the considered cases) with a limited cost in terms of area and performance degradation.

In the present paper, we propose a new design flow for the analysis and the implementation of circuits on Flash-based FPGAs hardened against Single Event Effects (SEEs). The solution we developed is based on two phases: 1) an analyzer algorithm able to evaluate the propagations of SETs through logic gates; 2) a hardening algorithm able to place and route a circuit by means of optimal electrical filtering and selective guard gates insertions. The effectiveness of the proposed design flow has been evaluated by performing hardening on seven benchmark circuits and comparing the results using different implementation approaches on 130nm Flash-based technology. The obtained results have been validated against radiation-beam testing using heavy-ions and demonstrated that our solution is able to decrease the circuits sensitivity versus SEE by two orders of magnitude with a reduction of resource overhead of 83 % with respect to traditional mitigation approaches.

Transient faults can affect the behavior of electronic systems, and represent a major issue in many safety-critical applications. This paper focuses on Control Flow Errors (CFEs) and extends a previously proposed method, based on the usage of the debug interface existing in several processors/controllers. The new method achieves a good detection capability with very limited impact on the system development flow and reduced hardware cost: moreover, the proposed technique does not involve any change either in the processor hardware or in the application software, and works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.

Detecting the effects of transient faults is a key point in many safety-critical applications. This paper explores the possibility of using for this purpose the debug interface existing today in several processors/controllers on the market. In this way one can achieve a good detection capability with respect to control flow errors with very small latency, while the cost for adopting the proposed technique is rather limited and does not involve any change either in the processor hardware or in the application software. The method works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method.