This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2$\micro\hbox{m}$-diameter, 6$\micro \hbox{m}$-height through-silicon vias (TSVs) and$3.4\nbsp\micro\hbox{m}$-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

Voltage overscaling for power reduction in RF systems has been limited by the need to maintain sufficient overscaling guard bands to ensure that minimum signal quality requirements of the end to end communication link are met. In this paper, we propose error control mechanisms at the symbol (probabilistic symbol remapping) and bit levels (code based correction and feedback) that allow more aggressive voltage overscaling than is possible otherwise. Error control feedback is used to continuously monitor and control the tuning knobs of the front end RF circuitry to trade off signal quality vs. power consumption. Real time image and voice data is used to demonstrate this concept. Significant power savings is achieved using the proposed scheme while maintaining minimum signal quality as required by the wireless communication link.