Thread divergence frequently occurs in various GPGPU applications while parallel threads encounter branching, especially for multimedia algorithms involving high-level image processing and computer vision algorithms. Either predicate or branch instruction degrades the parallel processing performance as a result of synchronization cost. In this work, we propose a configurable thread compaction unit (TCU) to relieve such execution overhead. Through early-stage compacting divergent threads by evaluating a compacting function with a compacting map, TCU can prevent redundant executions caused by predicate instruction, or repetitively invoking processors to fetch instructions and validate effective branches. Our simulation results show that, with TCU, GPUs can improve up to 24.5x and 1.8x performance for Viola-Jones face detection framework compared to predicate and branch instruction. Furthermore, 4.3x and 1.4x improvement in salient region linear feature extraction can be achieved as well. Finally, cache issue in TCU architecture is also discussed in detail.

Arithmetic transformations using carry-save adders have been exploited recently in design automation but existing transformation approaches only optimize combinatorial functions. Most applications need synchronous circuits and it is known that techniques that move the positions of the registers, such as retiming, can significantly reduce the cycle time of a synchronous circuit. However, retiming disregards arithmetic transformations and its power is limited by the circuit topology. This work is the first to exploit carry-save arithmetic transformations together with the moving of the register positions. To enable such transformations, we first propose the use of a new multiple-vector signal representation. Next, we use multiple-vector signal representation as a common guide for all of our simultaneous carry-save arithmetic transformations with the moving of the register positions. Specifically, we propose, operation forward and operation backward carry-save transformations, which are transformations across register boundaries. We also propose operation duplicate and operation merge transformations to exploit the resource sharing and timing trade-offs in the implementation of a multiple-fanout network. Finally, we propose an efficient and effective heuristic that selectively applies a sequence of transformations to optimize the timing and the area of a synchronous circuit. Experimental results show that the proposed techniques significantly out-perform previous approaches.

This paper presents VLSI implementations of an 8-error correcting (255, 239) Reed-Solomon (RS) decoder architecture for the optical fibre systems. We present the RS decoders using Euclidean and modified Euclidean algorithms which are regular and simple, and naturally suitable for VLSI implementation. We investigate hardware complexity, clock frequency and data processing rate for those RS decoders. The RS decoder based on the modified Euclidean algorithm operates at a clock frequency of 75 MHz and has a data processing rate of 600 Mbits/s in 0.25-/spl mu/m CMOS technology with a supply voltage of 2.5 V.

Traditional approaches to the distributed simulation of digital designs are limited in that they are inefficient and prone to deadlock for systems with feedback loops. This paper proposes an asynchronous distributed algorithm to the simulation and verification of behavior-level models and describes its implementation on an actual loosely-coupled parallel processor. The approach is relatively efficient for realistic digital designs and mathematically shown to be deadlock free. Additionally, it includes a new technique for modeling the timing of digital systems that guarantees the accuracy of the simulation results. In the discipline of computer-aided design of digital systems, a behavior model refers to a compact and executable representation of the activities of a complex digital component or an entire digital system such as the Motorola 68000, expressed through a high-level hardware description language such as ADLIB or VHDL. Behavior models are popular because of their flexibility; however, they execute excruciatingly slow on uniprocessor computers. The approach presented in this paper has the potential to significantly reduce the execution time through concurrent execution on multiple processors.>

Discusses the specification and automated synthesis of mixed synchronous/asynchronous systems in the context of a VHDL-based design environment. We propose a flexible paradigm for describing asynchronous behavior in VHDL that supports (1) the description of behavior as a signal transition graph (STG), (2) its expression in the form of an initializable edge-triggered finite state machine, and (3) the specification of a level-sensitive asynchronous finite state machine. An important feature is that free-running signals such as clocks can be included in the asynchronous specifications. The input specification, consisting of timing diagrams and/or the behavior and interface specifications for a set of interacting processes, is mapped into an appropriate combination of hazard-free asynchronous circuits and synchronous circuits.>

A new, fast fault simulator called differential fault simulator, DSIM, for sequential circuits is described. Unlike the concurrent fault simulation, DSIM simulates each machine by simulating its machine differences from the other machine just simulated instead of simulating its input differences from the previous status of the same machine. In this manner, DSIM simulates each machine (good or bad) separately for every test vector. Therefore, DSIM dramatically reduces the dynamic memory requirement and the overhead in the memory management in the concurrent fault simulation. Also unlike the single fault propagation which simulates each bad machine by simulating its machine difference from the good machine, the overhead to restore the good machine status before each bad machine simulation is eliminated in DSIM. Our experiments show that DSIM runs 3-12 times faster than an existing concurrent fault simulator and an experimental single fault propagation simulator. Furthermore, owing to the straightforward operations, DSIM is very easy to implement and maintain. Implementation consists of less than 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential test generation system, STG. Currently DSIM uses a zero-delay timing model, while inclusion of other delay models is under development.

Hopfield decision neural nets have been claimed to be good for solving a class of optimization problems such as the traveling salesman's problem. A study was undertaken to determine if these techniques were applicable to the many optimization problems that occur in VLSI circuit design and layout. Module placement was chosen as a representative problem. It was observed that the convergence process closely resembles that of greedy hill climbing algorithms. Apart from the known problems of long simulation times and hardware implementation complexity, it was noted that the quality of solution was mediocre, at best, and highly sensitive to network parameters. Various modifications were attempted, none of which significantly improved the result. It is concluded that Hopfield neural nets do not, in their present form, provide an interesting solution to this class of CAD problems.

The authors examine the limitations of the timing semantics in the conventional behavioral simulators and present a preemptive scheduling mechanism for accurate behavioral simulation results. They consider two signal transitions at the input ports of a component, where the second input transition arrives later than the first transition. The first and second input transitions cause first output signal transitions O/sub 1/ and O/sub 2/, respectively, to be generated at the output port of the component. When the logical values of O/sub 1/ and O/sub 2/ conflict with each other and O/sub 1/ arrives later than O/sub 2/, O/sub 1/ is preempted by O/sub 2/. In addition, an input signal to a component whose pulse duration is smaller than the inertial delay of the component, T/sub mip/, is discarded during simulation. Empirical measures for T/sub mip/ relative to the high-to-low and low-to-high propagation delays of the component for TL (transistor-transistor logic), NMOS, and CMOS technologies are presented. This approach has been implemented in the ADLIB-SABLE simulator at Stanford University.>