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Dmitri E. Nikonov

dblp:81/10670 · DBLP profile ↗
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4ranked-venue papers
1as first author
0since 2021 · last 2019
0000-0002-1436-1267ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Emerging computing paradigms · 57% Integrated circuit design · 38% Electronic design automation · 5%

Topics — the 7 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
beyond-CMOS computing
0.312017
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited · DAC 2017
Emerging computing paradigms › beyond-CMOS computing
beyond-CMOS devices
0.212013
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking · Proc. IEEE 2013
Integrated circuit design
digital circuit design
0.212013
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking · Proc. IEEE 2013
Integrated circuit design › semiconductor device modeling
nanoscale device modeling
0.112008
Modeling of Nanoscale Devices · Proc. IEEE 2008
Emerging computing paradigms › quantum computing › quantum simulation
quantum transport simulation
0.112008
Modeling of Nanoscale Devices · Proc. IEEE 2008
Electronic design automation › design methodology
circuit design methodology
0.012013
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking · Proc. IEEE 2013
Integrated circuit design › semiconductor devices
semiconductor device physics
0.012008
Modeling of Nanoscale Devices · Proc. IEEE 2008

Methods — techniques the papers use, named apart from their topics

switching time estimation · 0.2energy estimation · 0.2device benchmarking methodology · 0.2circuit area estimation · 0.2nonequilibrium green's function · 0.1landauer-buttiker formalism · 0.1
YearPublicationVenuePosition
2019 An Energy-Efficient Classifier via Boosted Spin Channel Networks
abstract
With diminishing energy and delay benefits via CMOS scaling, there is much interest in exploring the use of alternative state variables such as electronic spin. Multiple research efforts are underway exploring both Boolean and non-Boolean design space using spin devices in order to make their energy and delay benefits competitive to CMOS. In this paper, we propose spin channel networks (SCNs) - spin-based circuits that exploit exponential decay of spin current to efficiently realize multi-bit dot product computation. We show that proposed SCNs can be employed with adaptive boosting (AdaBoost) learning algorithm to efficiently realize a binary classifier for breast cancer detection. The proposed SCN implementation achieves 112× and 14× lower energy per decision compared to the conventional all spin logic (ASL) and 20nm CMOS designs, respectively, for identical decision throughput.
Ameya Patil 0001, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Naresh R. Shanbhag
ISCAS3
2017 A Systems Approach to Computing in Beyond CMOS Fabrics: Invited
abstract
No abstract available.
Ameya Patil 0001, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Lawrence T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
DAC11
2013 Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking
abstract
Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the complementary metal-oxide-semiconductor (CMOS) roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time, and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.
Dmitri E. Nikonov, Ian A. Young
Proc. IEEE1
2008 Modeling of Nanoscale Devices
abstract
We aim to provide engineers with an introduction to the nonequilibrium Green's function (NEGF) approach, which is a powerful conceptual tool and a practical analysis method to treat nanoscale electronic devices with quantum mechanical and atomistic effects. We first review the basis for the traditional, semiclassical description of carriers that has served device engineers for more than 50 years. We then describe why this traditional approach loses validity at the nanoscale. Next, we describe semiclassical ballistic transport and the Landauer–Buttiker approach to phase-coherent quantum transport. Realistic devices include interactions that break quantum mechanical phase and also cause energy relaxation. As a result, transport in nanodevices is between diffusive and phase coherent. We introduce the NEGF approach, which can be used to model devices all the way from ballistic to diffusive limits. This is followed by a summary of equations that are used to model a large class of structures such as nanotransistors, carbon nanotubes, and nanowires. Applications of the NEGF method in the ballistic and scattering limits to silicon nanotransistors are discussed.
M. P. Anantram, Mark S. Lundstrom, Dmitri E. Nikonov
Proc. IEEE3