Advances in microelectronics and the evolution of IoHT devices allow the collection and, consequently, generation of a greater volume of health data, intensifying the need for robust data privacy solutions. Traditionalk-anonymity-based anonymization techniques often suffer from high information loss, especially as the anonymity parameter k increases. To address these challenges, this article proposes Generalization Firstk-Member Clustering (GFKMC), a novelk-anonymity method that applies early generalization to quasi-identifiers, reducing computational overhead and minimizing information loss. Unlike traditional methods (e.g., Mondrian, Top-Down Greedy (TDG), and Clustering-Based (CB)), GFKMC maintains nearly constant information loss (≈ 25%) across varyingkvalues and better preserves machine learning model performance, especially in lowkscenarios. Empirical evaluations demonstrate that GFKMC outperforms baseline methods by significantly minimizing the trade-off between data utility and privacy. Moreover, GFKMC preserves the performance of machine learning models more effectively.

Coarse-Grained Reconfigurable Architectures (CGRAs) have been the subject of extensive research due to their balance between performance, energy efficiency, and flexibility. CGRAs must be capable of executing a dataflow graph (DFG), which depends on a compiler producing quality valid mappings with feasible running time performance and portable mapping DFGs on different CGRA architectures. Machine learning-based compilers have shown promising results by presenting high quality and performance but offer limited portability. Moreover, some approaches do not explore efficient placement methods or do not demonstrate whether scaling to more challenging, less connected architectures. This paper presents SmartMap, an architecture-agnostic framework that uses an actor-critic reinforcement learning method applied to a Monte-Carlo Tree Search (MCTS) to learn how to map a DFG onto a CGRA. This framework offers full portability using a state-action representation layer in the policy network instead of a probability distribution over actions. SmartMap uses a graph traversal placement method to provide scalability and improve the efficiency of MCTS by enabling more efficient exploration during the search. Our results show that SmartMap has 2.81x more mapping capacity, a 16.82x speed-up in compilation time, and consumes fewer resources compared to the state-of-the-art.

The increasing volume of sensitive data generated by various domains demands robust approaches to privacy protection. Anonymization based on k-anonymity stands out for mitigating the risks of re-identification of personal data. However, the impact on the performance of machine learning models is commonly neglected. This work proposes a novel comparative method to evaluate the effects of anonymization on the performance of machine learning models, considering privacy, information loss, and performance metrics. The empirical results show how generalization based on k-anonymity impacts federated learning solutions and provides insights for developing and improving methods that reconcile data privacy and efficiency.

The growing prevalence of interconnected devices in the Internet of Things (IoT) has intensified concerns about data security and user authentication. This study investigates a multimodal biometric authentication approach integrating Photoplethysmography (PPG) and Electroencephalography (EEG) signals to enhance accuracy and robustness. We adapted a previously validated PPG and Electrocardiogram (ECG) model, replacing the ECG component with an EEG-based method optimized through hyperparameter tuning. Our findings demonstrate that combining brain and heart signals improves authentication performance, with the multimodal approach surpassing unimodal methods. The optimized model achieved a precision of $97.05 \%$, a recall of $97.19 \%$, a F1-Score of $96.96 \%$, and an accuracy of $97.05 \%$, highlighting the potential of EEG-PPG fusion in secure biometric authentication.

ABSTRACT High‐performance computing demands efficient and scalable interconnections. Although crossbar networks offer high parallel bandwidth, their costs are prohibitively expensive. Multi‐stage networks provide scalability with cost, yet they may block certain routing patterns. Rearrangeable multistage networks (RMNs) have emerged as a cost‐effective solution, enabling internal connection rearrangements to make all paths accessible without network blocking. However, discovering optimal rearrangement strategies remains a challenge for unblocking large‐scale (256 connections) reconfigurable networks. We advance the state of the art by effectively managing workloads with over 50% without blocking. When nearly all connections are required, we introduce routing strategies to rearrange existing connections. In the presence of multicast, where the configuration space exceeds , we propose novel strategies employing simulated annealing for placement and Monte Carlo tree search for routing to prioritize multicast connections, which simultaneously maximize the number of connections by minimizing conflicts and reducing the number of extra stages. To the best of our knowledge, we first demonstrate that the Benes network is not rearrangeable under multicast conditions. We propose exploring the rearrangeability of shuffle exchanges with additional network stages.

ABSTRACT This work presents the development of reconfigurable processing units capable of encapsulating various operations to design new domain‐specific reconfigurable accelerators. These processing units are known as coarse‐grained operators because they can execute multiple operations. We validated the new operators within the HPCGRA framework, a design environment for creating custom coarse‐grained reconfigurable arrays that run as a virtual layer on commercial field‐programmable gate arrays. The environment is parameterized and employs an intermediate portable format that abstracts away low‐level specific bitstream details, enabling hardware‐agnostic reconfiguration. In this paper, we present three case studies. The first is a domain‐specific accelerator for the K‐means algorithm, which can be entirely reconfigured in less than 2.34 ms to explore various clustering values and attributes, achieving up to 159 Gop/s performance for considering 8 features. The reconfigurability of our accelerator has no impact on performance compared to static versions implemented directly in HLS and RTL. The second case study extends K‐means with a Gini calculation operator for dimensionality reduction, quantization, and quality classification, achieving up to 278 Gops/s. The third case study presents a systolic matrix multiplier, demonstrating the versatility of the environment for designing different architectural domains.

Technological advances enable the integration of Internet of Things (IoT) devices to perform continuous and proactive patient monitoring. These devices collect a large volume of sensitive data that requires privacy. Anonymization provides privacy by removing or modifying information that identifies an individual. However, traditional anonymization techniques, such as k-anonymity, depend on a fixed and pre-defined k value, susceptible to attribute disclosure attacks. This article presents Dynamic Anonymization by Separatrices (DAS), an approach for defining the ideal value k and for dynamic grouping of data to be anonymized using separatrices measurements. Results show that the proposed approach efficiently mitigates attribute disclosure attacks.

In an increasingly connected world, ensuring security in e-health is a challenge. Traditional security models based on perimeter trust are insufficient to guarantee the protection of these systems. Since these models work by directly assigning trust to the user, the entire network becomes vulnerable if the user’s credentials or device are compromised. Thus, this work proposes and evaluates a model based on Zero Trust to considerably increase security in e-health environments. The proposed model uses privilege reduction and user confidence analysis to perform access control. The evaluation follows simulation in different scenarios, assessing their assertiveness in delegating access. The results show the effective detection of anomalies in accesses by the model.

NFV and SDN enable flexibility and programmability at the data plane. In addition, offloading packet processing to a hardware saves processing resources to compute other workloads. However, fulfilling requirements such as high throughput and low latency with a flexible and programmable data plane is challenging. This paper introduces eBPFlow, a platform for seamlessly accelerating network computation. It builds upon eBPF. eBPFlow combines flexibility and programmability in software with high performance using an FPGA. We implemented our system on the NetFPGA SUME, performing tests on a physical testbed. We built a range of NFs. Our results show that the eBPFlow supports offloading of NFs with throughput at the line rate, latency between$20~\mu \text{s}$and$40~\mu \text{s}$, communication with host, and consumption of 22 W. Moreover, eBPFlow processes 12.05 Mpps more than the kernel. eBPFlow has a throughput of 2.59 Gbps higher than the hXDP, a system similar to eBPFlow.

Abstract Cloud FPGAs provide new energy‐efficient opportunities to design dataflow accelerators. Nevertheless, FPGAs still have challenges to overcome for widespread usages, such as programmability, compilation time (minutes to hours), and hardware knowledge, mainly because it is highly challenging for beginners to learn and use FPGAs. The READY tool recently provides compilation time reduction to the range of microseconds using a CGRA overlay and a friendly, high‐level C++ interface for the Intel/Altera HARPv2 FPGA cloud platform. However, the HARPv2 is not available in any commercial cloud platform. This work extends READY by creating the fast flow cloud framework (FFC). First, FFC offers a simple browser‐based graphical interface for less experienced FPGA users. Second, we improve the CGRA overlay portability to include Xilinx FPGAs and a transparent design flow to deploy in the widespread commercial Amazon AWS F1 cloud. Third, we improve the CGRA reconfiguration engine. Also, we compare the overlay performance of HARPv2 and AWS F1 to an eight‐thread XEON processor. Finally, the framework is open‐source for collaborative development and has clearly defined application programming interfaces for future extensions.

Abstract This work explores the placement and routing of machine learning applications' dataflow graphs on different heterogeneous coarse‐grained reconfigurable architectures (CGRA). We analyze three different types of processing element (PE) heterogeneity, the first concerning the interconnection pattern, the second being on the kind of operations a single PE can execute, and the last concerning the PE buffer resources. This analysis aim to propose a fair reduction to the overall cost in comparison to the homogeneous CGRA architecture. We compare our results with the homogeneous case and one of the state‐of‐the‐art tools for placement and routing (P&R). Our algorithm executed, on average, 52% faster than VPR 8.1 (Versatile Place and Route), which is an open‐source academic tool designed for the FPGA placement and routing phases, reaching better mapping in 66% of cases and achieving the same results in 26% of cases. Furthermore, a heterogeneous architecture reduces the cost without losing performance in 76% of the cases considering multiplier heterogeneity. We propose a novel heterogeneous buffer architecture that minimizes the buffer resources by 56.3% for K‐means dataflow patterns. We also show that a heterogeneous border chess architecture outperforms a homogeneous one. In addition, our mapping reaches optimal instances of single tree dataflows compared to classical Lee/Choi and H‐trees.

Summary Gene regulatory networks (GRN) are dynamic models in time and space. These models are used to predict diseases and in drugs research. GRN models are discrete, and Boolean graphs can efficiently represent them. However, GRN algorithms explore a large solution space with high computational complexity. This work proposes efficient FPGA‐based accelerators to implement two GRN algorithms: attractor computation and Derrida plot. Nevertheless, FPGA accelerator design and deployment are still a challenge. This work presents an accelerator design framework for AWS Amazon FPGA cloud. The framework simplifies the software (SW) and hardware (HW) generation for GRN accelerators. The user provides a high‐level model for the Boolean GRN, and our tool automatically creates AWS‐ready‐to‐deploy software and hardware components. For the attractor and the Derrida plot computation, the proposed FPGA accelerators are on average and faster than a V100 GPU.

Finding the minimum register bank is an optimization problem related to the synthesis of hardware. Given a program, the problem asks for the minimum number of registers plus their minimum size, in bits, that suffices to compile said program. This problem is NP-complete; hence, usually solved via heuristics. In this paper, we show that this problem has an optimal solution in polynomial time, as long as swaps can be inserted in the program to move variables across registers. This observation sets a lower bound to heuristics that minimize the size of register banks. We have compared the optimal algorithm with two classic heuristics. Our approach uses, on average, 6 to 10% less bits than that previous work.

The immediate and new challenges of the current Covid-19 pandemic have made it hard for all of us; in this work in progress as an innovative practice, we look to both leverage the challenges and share our work so that others might see some benefit to these times and improve their courses. In particular, our focus is on creating automated tools to physically create exams and sample code for Digital Systems and Computer Architecture courses. Additionally, we focus on shifting, traditional in-person labs to online, personalized formats for Digital Systems and Embedded Systems so that both educator and learner can still provide/experience virtual computer engineering education. We focus on three courses (Digital System Design, Computer Architecture/Organization, and Embedded System Design) as they are fundamentally driven by the implementation and execution of “algorithms”. From this starting point, we have created tools to generate sample code and exams, and have found means to virtualize labs and hands-on activities. In particular, we have created Python tools that allow educators to personalize code and problems, create these codes/problems (as text files or incorporated in word documents), and email these documents to students. This provides the means to create problems and code examples that are different from their peers and can be assessed on a per individual basis to alleviate some of the challenges with live and proctored exams. Additionally, we have found tools and methods for students to virtually perform the hands-on portion of these three subjects without the need for traditional lab equipment. This requires students to spend less than 100 USD worth of equipment and software. Our goal is to share these resources and our methodologies to help in this time of crisis. Additionally, these tools and methods have forced us to innovate our teaching, and we will, likely, use these tools and methods in the future. We share these tools in hope that the computer engineering education community will join this process to help us all improve our student's education.

The performance of Attribute-Based Access Control is negatively affected by communications over the network between the policy decision point and policy information point for each attribute request. Attribute caching is a standard solution to mitigate this problem. However, due to the dynamic nature of attributes, the cost to keep them refreshed increases for each new attribute replica. This paper presents a method that predicts each request and anticipate the positioning of the attributes closer to the requester exploring the tradeoff between the cost of creating a new replica versus updating a replica. The proposed method follows a two-way approach, where it deals with the current attribute requests and their estimates based on user mobility and the best positions for the attributes. Through trace-driven simulations, considering traces from a large university campus, the method shows a reduction of up to 80% in the number of hops to get the needed attributes at negligible refreshment cost.

Google Colab is a cloud Jupyter notebook widespread used to teach machine learning by writing text explanations and Python codes through the browser. This work introduces new Colab extensions to teach logic circuit design, Verilog language, processor, and GPU architectures. Colab allows us to share reproducible experiments on the Web. The students become motivated to do laboratory assignments without download/configure software packages and dependencies on their computers. Furthermore, almost all universities had to shut down due to the COVID-19 pandemic, forcing us to adapt to virtual learning scenarios. Colab provides portability and accessibility since it can even run on smartphones. The lab assignments include intermediate guided exercises, text explanations, figures, online quizzes, problem sets, and basic hands-on tasks. We develop a simple setup for Icarus Verilog, PyEDA, CUDA, Valgrind, and Gem5 frameworks. This work presents Verilog teaching and computer architecture simulation insights by using Valgrind and Gem5, and GPU computer architecture profiling at the thread and instruction assembly level.

The Nanomagnetic Logic (NML) is a promising new technology that can build low-power devices at room temperature. Furthermore, this technology allows mixing logic and memory on the same device. The creation of Electronic Design Automation (EDA) tools and flows is an essential step towards developing NML for integrated designs. There is plenty of room for creating new EDA methodologies for this kind of emerging nanotechnologies since the scarce number of works in this field. Standard cells is an important step in this context since they strongly relate to the routing and placement algorithms. This work presents NMLib, an NML cell library developed for the NMLSim 2.0 simulator. In contrast to CMOS, the NML features require logic cells and interconnection cells, since all circuit is developed using the same building block. Moreover, we present a full-adder, and a ripple carry adder circuit designs using NMLib to demonstrate NMLib feasibility.

We ask the question, “should High-level Synthesis (HLS) design be part of an undergraduate computer engineering education while learning digital system design?”. Current trends in industry include an increasing demand for engineers who can build FPGA systems. FPGAs, just like other chips, continue to improve in terms of complexity, speed, available resources, and new features. The design complexity for using an FPGA continues to grow and Hardware Description Languages (HDLs), though a step up in design efficiency compared to schematic design, is a low-level approach akin to assembly language for programmers, and HDLs limits the productivity of an engineer. HLS tools, such as Legup, Intel HLS, and Xilinx's Vivado attempt to provide designers with a higher-level design abstraction providing a means to describe their computation in high-level languages - such as C. As these tools become more mainstream in industry, when should education follow? In this work, we explore how HLS tools might be used by an undergraduate by looking at exemplar designs, a simple RISC-V processor and a basic C loop, and implementing the design in both HDL and HLS. We then analyze the FPGA cost of each implementation. Next, we provide a philosophical discussion based on this experience on what the pros and cons of moving students to HLS design abstraction level are.

Coarse-grained reconfigurable architectures (CGRA) are a power-efficient approach for hardware accelerators. However, there are few EDA tools for CGRA. We develop hardware-based placement and routing (P&R) for fully-pipelined CGRA mapped as an FPGA overlay. The key idea is to use the available FPGA resources to replicate several mapping units, thus exploring parallel execution, area/execution time trade-offs, and achieving near-optimal mapping solutions. Furthermore, our P&R provides portability and an incremental run-time approach. In comparison to VPR and CGRA-ME tools and a time-multiplexer approach, our spatial mapping reduces the P&R execution time, and it improves the performance up to hundreds of Gops/s by using fully-pipelined architectures.

Coarse grain reconfigurable architectures (CGRAs) are an emerging hybrid computational architecture that has the parallel customization benefits of low-level logic devices, such as FPGAs and ASICs, while the relative coarseness of these architectures makes CGRAs easier to design for, which is more similar to the traditional processor. In the process of mapping designs to CGRAs, flexible, fast, and adaptive placement and routing (P&R) is fundamental in order to implement efficient run-time reconfigurable frameworks. It is well-known that P&R is an NP-complete problem, and thus, solutions rely on heuristics to achieve quality results with acceptable execution times. CGRA P&R has different constraints compared to traditional VLSI P&R, e.g., path latency balancing and modulo scheduling of loops. In this work, we propose a graph-based P&R approach that uses graph traversals to map designs to CGRAs. Additionally, we parallelize our approach with a graph-based greedy heuristic that executes on a GPU. We compare our proposed P&R approach with the CGRA-ME framework, which implements simulated annealing and integer linear programming placement algorithms. Our results show that this new approach can generate optimal mappings and improve the execution run-time up to several orders of magnitude. Furthermore, considering spatial mapping at the millisecond scale, our GPU approach is one order of magnitude faster compared to the state-of-the-art tool VPR.

Coarse-grained reconfigurable architecture (CGRA) mapping involves three main steps: placement, routing, and timing. The mapping is an NP-complete problem, and a common strategy is to decouple this process into its independent steps. This work focuses on the placement step, and its aim is to propose a technique that is both reasonably fast and leads to high-performance solutions. Furthermore, a near-optimal placement simplifies the following routing and timing steps. Exact solutions cannot find placements in a reasonable execution time as input designs increase in size. Heuristic solutions include meta-heuristics, such as Simulated Annealing (SA) and fast and straightforward greedy heuristics based on graph traversal. However, as these approaches are probabilistic and have a large design space, it is not easy to provide both run-time efficiency and good solution quality. We propose a graph traversal heuristic that provides the best of both: high-quality placements similar to SA and the execution time of graph traversal approaches. Our placement introduces novel ideas based on “you only traverse twice” (YOTT) approach that performs a two-step graph traversal. The first traversal generates annotated data to guide the second step, which greedily performs the placement, node per node, aided by the annotated data and target architecture constraints. We introduce three new concepts to implement this technique: I/O and reconvergence annotation, degree matching, and look-ahead placement. Our analysis of this approach explores the placement execution time/quality trade-offs. We point out insights on how to analyze graph properties during dataflow mapping. Our results show that YOTT is 60.6 , 9.7 , and 2.3 faster than a high-quality SA, bounding box SA VPR, and multi-single traversal placements, respectively. Furthermore, YOTT reduces the average wire length and the maximal FIFO size (additional timing requirement on CGRAs) to avoid delay mismatches in fully pipelined architectures.

We present an approach to teach RISC processor design for an undergraduate computer architecture course specifically aimed to reduce the gap between a high-level datapath block diagram and a complete Verilog code specification. We propose a graphical approach designed to develop an understanding of the MIPS processor organization at the Verilog structural level by using an online browser-based simulator, from a single cycle design to pipeline design. The students are lead through a series of examples, step by step, and they can actively be involved in the processor design process. We believe that the best choice should not introduce excessive complexity that becomes a barrier in describing the interconnection of a high-level diagram and the Verilog implementation code.

Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

In this work, we propose a framework called REconfigurable Accelerator DeploY (READY), the first framework to support polynomial runtime mapping of dataflow applications in high-performance CPU-FPGA platforms. READY introduces an efficient mapping with fine-grained multithreading onto an overlay architecture that hides the latency of a global interconnection network. In addition to our overlay architecture, we show how this system helps solve some of the challenges for FPGA cloud computing adoption in high-performance computing. The framework encapsulates dataflow descriptions by using a target independent, high-level API, and a dataflow model that allows for explicit spatial and temporal parallelism. READY directly maps the dataflow kernels onto the accelerator. Our tool is flexible and extensible and provides the infrastructure to explore different accelerator designs. We validate READY on the Intel Harp platform, and our experimental results show an average 2x execution runtime improvement when compared to an 8-thread multi-core processor.

The constant increase in the number of accidents and traffic jams negatively impacts several areas, including the economy, environment, and health. Since most monitoring systems require high installation and maintenance costs, especially because they depend on a central element, systems based on decentralized infrastructure have emerged as an attractive option. However, these systems cannot guarantee the synchronization between the devices' clocks since there is no centralized element. This paper presents DOCTraMS, a system that monitors and disseminates traffic conditions using a decentralized infrastructure. On-board units and roadside units do not need to be interconnected or connected to a central computer. These elements exchange information to update their tables that describe the traffic conditions of each road segment. To validate DOCTraMS, we have implemented a real IEEE 802.11 b/g prototype at Universidade Federal do Rio de Janeiro Campus. Moreover, we have simulated larger scenarios using NS-3 with traffic data from São Paulo, Brazil. When compared with a GPS, our system accuracy is higher than 90% in all scenarios.

Quantum-dot Cellular Automata (QCA) is a field-coupled nanotechnology which might enable design with high performance and extraordinary low energy dissipation. Infor-mation processing and flow in QCA is controlled by external clocks, which requires a proper synchronization already during circuit design phase. In this paper, we discuss the fundamental differences between local and global synchronicity in QCA circuits. Further, we show that it is possible to relax the global synchronicity constraint and discuss the consequent impact on the design performance. Simulation results indicate that the design size can be reduced by about 70% while the throughput performance declines by similar values.

The QCA gate-level design introduces new challenges to the traditional mapping, placement, and routing flow. First, the wires consume more than 90% of total area. In addition, even a combinational circuit requires a clock scheme, and all internal paths should be balanced. This work proposes a novel approach to automatically map a gate-level circuit onto a QCA layout by using a merge overlapping approach, and a universal clock scheme to provide scalability. First, the circuit is decomposed into a set of overlapping subgraph partitions. This decomposition is guided by reconvergent paths. For each subgraph, more than one customized QCA layout cell is generated on-the-fly. During the last step, a merge overlapping algorithm rebuilds the entire circuit to produce the final layout. All inter and intra-partition wires should be balanced according to the adopted clock scheme. Our approach reduces the total area in more than 50% in comparison to a previous approach based on standard-cell QCA libraries. Finally, all layouts were validated on QCA Designer simulator to verify the design rules.

QCA (Quantum-dot Cellular Automata) is a promising new technology with low power consumption and high speed that allows the design of nanoscale integrated circuits. The 3-input/1-output majority gate is the basic building block in QCA circuits. This work presents a new design of a multi-output, 5-input majority gate. Our proposed gate is quite useful because its outputs can present different configurations with several logical functions at once, enabling the design of smaller circuits. Also, the proposed gate is a feasible solution for the recently proposed USE (Universal, Scalar and Efficient) clocking scheme. In order to demonstrate the flexibility and area efficiency of our 5-input majority gates we implement two designs: a full adder and a RAM cell block. These designs have been implemented using a free and a regular (USE) clock schemes. Our results show area reductions up to 50% compared to state-of-the-art designs.

Monitoring underwater environments is still a hard and costly task. Indeed, electromagnetic and optical waves suffer high attenuation, being absorbed in a few meters and even acoustic communication presents low throughput and high bit error rate. Most of the existing approaches to enhance underwater communication performance relies on developing acoustic modems, multiple access to the communication channel and, data routing. In this paper, we present COPPER: a COoperative Protocol for PERvasive Underwater Acoustic Networks. COPPER synchronously/asynchronously works on top of TDMA method combined with an ARQ scheme based on selective repeat technique. It uses idle sensor nodes as relay nodes, enhancing communication space diversity. Our simulations show that, when compared to a non-cooperative protocol, COPPER enhances overall network performance metrics. For instance, it reduces packet error rate by 28.32% and increases goodput by 16.87% while spending less than 1% more energy.

Recent years have seen a surge in the popularity of Field-Programmable Gate Arrays (FPGAs). Programmers can use them to develop high-performance systems that are not only efficient in time, but also in energy. Yet, programming FPGAs remains a difficult task. Even though there exist today OpenCL interfaces to synthesize such hardware, higher-level programming languages, such as Java, C# or Python remain distant from them. In this paper, we describe a compiler, and its supporting runtime environment, that reduces this distance, translating functional code written in Java to the Intel HARP platform. Thus, we bring two contributions. First, the insight that a functional-style library is a good starting point to bridge the gap between high-level programming idioms and FPGAs. Second, the implementation of this system itself, including the compiler, its intermediate representation, and all the runtime support necessary to shield developers from the task of transferring data back and forth between the host CPU and the accelerator. To demonstrate the effectiveness of our system, we have used it to implement different benchmarks, used in image processing and data-mining. For large inputs, we can observe consistent 20x speedups over the Java Virtual Machine across all our benchmarks. Depending on the target function that we compile, this speedup can achieve 280x.

Health monitoring over wireless networks is at the same time increasingly popular and a challenging task. In fact, in a medical environment, the high density of wireless devices leads to an extensive amount of co-channel interferences, imposing risk to patients' life due to poor network performance (e.g. high latency and packet loss rate). In this work, we present a DynamiC distributed Channel Allocation (DCCA) protocol. DCCA takes into account the existence of co-located wireless body area networks (WBANs) and multiple base stations in a single medical environment. In other words, DCCA avoids co-channel interference and offers workload balancing among base stations by dynamically allocating channels based on a greedy solution to the graph-coloring problem. Simulation results from medical environment scenarios show that DCCA improves the quality of communication when compared with other representative frequency- allocation protocol. On average, DCCA increases 30% the network goodput and reduces 40% network latency.

Measurement and tracking have crucial roles in Software-Defined Networks (SDNs). Unfortunately, most of procedures and techniques to perform measurements and monitoring tasks are implemented in software at network end-hosts. Despite the large use, a software based approach generates imprecision, high costs, and makes monitoring more difficult. In this paper, we extend OpenFlow switch to implement a measurement architecture for SDN. Our system performs measurements in a simple and scalable way without depending on end-hosts. It allows monitoring the performance at the granularity of flows. Moreover, our system also enables software-defined measurements can collect flow's statistics on the fly. We have prototyped our architecture on the NetFPGA platform and, as an initial case study, we have implemented a module to measure packet interarrival time. This module has been validated in a realistic testbed. Our results demonstrate that the proposed architecture presents a negligible difference when compared to measurements performed by software at end-hosts.

This work presents a methodology based on simulator developers to be applied in several courses as well as research activities. This proposal is also based on “The Cathedral and the Bazaar” lessons. First, good programmers know what to write, however great ones know what to rewrite. Students could learn by developing new components to be added to the current simulator. Second, any tool should be useful in the expected way, but a truly great tool lends itself to uses you never expected. The proposed simulator has been developed to teach digital circuits. However, it can be used in many other computing engineering fields. Third point is motivation, where the lessons are driven by the following principle: To solve an interesting problem, start by finding a problem that is interesting to you. Nowadays, we are surrounded by Internet of things, where the simulator engine could be connected to learn and to motivate the students. Image processing could be taught by connecting your web-cam and/or your mobile device camera to your simulator engine. Moreover, mobile phones and/or Arduino devices have a set of sensors that could be captured inside of the virtual simulator lab.

Dynamic Partial Reconfiguration (DPaR) enables efficient allocation of logic resources by adding new functionalities or by sharing and/or multiplexing resources over time. Placement and routing (P&R) is one of the most time-consuming steps in the DPaR flow. P&R are two independent NP-complete problems, and, even for medium size circuits, traditional P&R algorithms are not capable of placing and routing hardware modules at runtime. We propose a novel runtime P&R algorithm for Field-Programmable Gate Array (FPGA)-based designs. Our algorithm models the FPGA as an implicit graph with a direct correspondence to the target FPGA. The P&R is performed as a graph mapping problem by exploring the node locality during a depth-first traversal. We perform the P&R using a greedy heuristic that executes in polynomial time. Unlike state-of-the-art algorithms, our approach does not try similar solutions, thus allowing the P&R to execute in milliseconds. Our algorithm is also suitable for P&R in fragmented regions. We generate results for a manufacturer-independent virtual FPGA. Compared with the most popular P&R tool running the same benchmark suite, our algorithm is up to three orders of magnitude faster.

Dynamic partial reconfiguration enables efficient use of hardware resources by multiplexing system functionality in time. However, many challenges arise from partial reconfiguration implementation. The placement and routing (P&R) of the hardware modules is a computationally intensive task, and the state-of-art algorithms are not suitable to place and route modules at run-time. This paper makes several contributions: (1) Single Placement at run-time: we propose a novel P&R algorithm based on greedy heuristic where a single placement is performed at run-time in few milliseconds. (2) Implicit Graph Model: the FPGA is modelled as an implicit graph with a direct correspondence to the physical FPGA, and the P&R is performed as a graph mapping problem by exploring the node locality during the depth-first traversal. (3) Polynomial Placement: we show that even a single placement can be routed without critical path degradation. (4) Fragmented Regions: the graph approach is flexible, and it allows efficient placement even onto fragmented FPGA areas. Compared with the most popular P&R tool running the same benchmark suite our algorithm is on average 864x faster. Moreover, the bitstream for partial reconfiguration is also reduced by a factor of 4.

P2P live streaming are increasingly popular nowadays. Due to their popularity, these systems may be a target of attacks and opportunistic user behavior. In this paper, we address the pollution attacks in such systems. We present a pollution damage model and also analyze a reputation system as a tool to fight attacks in P2P live streaming systems. The model we propose evidences that attacks are harmful even in a system with a small number of polluters. In this case, peers must have more than 3 times network bandwidth than they should have in a system without polluters. Our experimental results on PlanetLab show that just check data integrity is not an effective protection. In this case, we observe a very high data loss rate. Finally, the reputation system is effective against pollution attack. When peers do not whitewash their identities, the reputation system quickly identifies polluters. In this case, the overhead and loss rate can be negligible. During a whitewashing, the new approach presents less than 20% overhead and 3% of loss.

The research of underwater sensor networks (UWSNs) is gaining attention due to its possible applications in many scenarios, such as ecosystem preservation, disaster prevention, oil and gas exploration and freshwater reservoirs management. The main elements of a UWSN are underwater sensor nodes (UWNs). In this paper we present HydroNode: a low cost, energy efficient, multipurpose underwater sensor node (UWN). Nowadays, to the best of our knowledge, there is no UWNs that is simultaneously low cost, low power, able to couple diverse types of sensors and educationally available. Thus, the objective of this paper is to fill this gap by describing the design of HydroNode, an underwater sensor node that fulfill all these requirements and can be used in various UWSNs applications. We used only commercial off-the-shelf components to build our underwater sensor node. Due to its multipurpose design, HydroNode can be used in different UWSNs, therefore aiding the research of UWSN system protocols, configurations and applications.

Low-power devices require energy-aware design and dynamic power management techniques to reduce the power consumption. Communication intensive devices make the decision of shutting down idle components very difficult, specially in wireless communication. This paper presents a new system-level dynamic power management technique to reduce the power consumption of communication intensive sensor nodes in wireless sensor networks. It analyzes the application-level information to determine the need for communication and to selectively shutdown hardware components, specially the radio. The hybrid automata framework is used to dynamically change duty cycles, making the best trade-off between energy conservation and quality of service, according to the application requirements. Simulation results reveal that application-level information is crucial to reduce power consumption and to increase the sensor node lifetime.

Power consumption became a crucial problem in the development of mobile devices, especially those that are communication intensive. In these devices, it is imperative to reduce the power consumption devoted to maintaining a communication link during data transmission/reception. The application of dynamic power management methodologies has contributed to the reduction of power consumption in general purpose computer systems. However, to further reduce power consumption in communication intensive real-time embedded devices, we have to consider the state of the computation and external events in addition to power management policies. In this paper we propose a model of an Extended Power State Machine (EPSM), where we adapt a Power State Machine to include the state of an embedded program in the power state machine formulation. This EPSM model is used to adapt the Quality of Service (QoS) in communication intensive devices to ensure low power consumption. In such development, a middleware layer fits in the system's architecture, being responsible for intercepting the data communication and implementing the EPSM. Also, a software tool was developed, allowing the Middleware Code to be generated based on the State Machine. A case study demonstrates the application of the proposed model to a real situation.