Hiroyasu Nishiyama

dblp:81/1487 · DBLP profile ↗
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4ranked-venue papers
3as first author
0since 2021 · last 2007
0009-0004-0174-0198ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 50% Processor architecture and microarchitecture · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel architecture
associative processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991
Processor architecture and microarchitecture › SIMD
parallel associative processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991
Parallel and multicore computing › parallel architecture
parallel processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991
Processor architecture and microarchitecture › SIMD
SIMD processor
0.011991
IXM2: A Parallel Associative Processor · ISCA 1991

Methods — techniques the papers use, named apart from their topics

associative processing · 0.0
YearPublicationVenuePosition
2007 Fast synchronization for quasi-immutable objects
abstract
Abstract Increasing synchronization performance is one of the most important factors for improving Java performance. We present the concept of quasi‐immutable objects and its application to implement fast synchronization primitives. Quasi‐immutable objects are usually used for read accesses, but they are rarely used for write accesses. Using these characteristics, we describe the optimization for a synchronized read sequence of quasi‐immutable objects. Our described method dynamically detects objects that are not written from critical sections of other threads, and applies the fast read sequence. The optimized read sequence enables the simultaneous execution of critical sections by multiple threads and reduces synchronization overhead. We implemented the described optimization on HotSpot Java VM. The experimental evaluations indicated that the optimization improved the performance of a micro‐benchmark up to a factor of 16 and SPEC benchmarks up to 31%. Copyright © 2007 John Wiley & Sons, Ltd.
Hiroyasu Nishiyama, Kei Nakajima
Concurr. Comput. Pract. Exp.1
2005 SecureC: Control-Flow Protection Against General Buffer Overflow Attack
abstract
Increasing damage from computer virus or worms creating significant problems worldwide. These malicious programs take advantage of computer vulnerabilities to distort the control-flow of the target system. Among these vulnerabilities, buffer overflow is most frequently used as a means of intrusion. To protect against buffer overflow attacks, we have developed a source-to-source translator called SecureC. It incorporates two novel protection methods, "shadow stack" and "code pointer protection" that prevent control-flow transfer caused by buffer overflow attacks. Evaluation using 11 SPEC CPU2000 benchmark programs showed that SecureC prevents buffer overflow attacks with only 6.1% performance penalty.
Hiroyasu Nishiyama
COMPSAC (1)1
2000 Pseudo-vectorizing Compiler for the SR8000 (Research Note)
Hiroyasu Nishiyama, Keiko Motokawa, Ichiro Kyushima, Sumio Kikuchi
Euro-Par1
1991 IXM2: A Parallel Associative Processor
abstract
Article IXM2: a parallel associative processor Share on Authors: Tetsuya Higuchi Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305 Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305View Profile , Tatsumi Furuya Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305 Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305View Profile , Kenichi Handa Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305 Electrotechnical Laboratory, 1-1-4 Umezono, Tsukuba, Ibaraki, Japan 305View Profile , Naoto Takahashi University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305 University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305View Profile , Hiroyasu Nishiyama University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305 University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki, Japan 305View Profile , Akio Kokubu New Media Development Associate, 1-4-28 Mita, Minato-ku, Tokyo, Japan 108 New Media Development Associate, 1-4-28 Mita, Minato-ku, Tokyo, Japan 108View Profile Authors Info & Claims ISCA '91: Proceedings of the 18th annual international symposium on Computer architectureApril 1991 Pages 22–31https://doi.org/10.1145/115952.115956Online:01 April 1991Publication History 5citation307DownloadsMetricsTotal Citations5Total Downloads307Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
Tetsuya Higuchi, Tatsumi Furuya, Ken'ichi Handa, Naoto Takahashi, Hiroyasu Nishiyama, Akio Kokubu
ISCA5