problem has become one of the dominant factors in determining system reliability. This problem is caused by high current density flowing in the metal interconnect. Therefore, current evaluation is a crucial concern in IC design. SPICE level circuit simulators are excellent for doing current calculation, however, their running time are too expensive to be used repeatedly in design synthesis loops. In this paper, we propose an efficient approach for the interconnect current calculation. This method is based on moment matching but does not need high order moments. It only needs traversing the RC tree once to get the mean current value of every segment, traversing the tree once more is enough for the RMS current calculation, and two more traversals is sufficient for the peak current calculation. We apply our method to a larger number of interconnects getting close-to-SPICE accuracy at significantly faster runtimes. In particular, applying the method to 17,387 wire segments in the clock tree of a commercial IC, we obtained that the average deviation error of mean current is 0.0569%, average RMS current error is 0.703 % and average peak current error is 6.552%. It took 28 hours for HSPICE to get current value of all the wire segments and it only took our method 156 seconds. I.

Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay value, the gate modeling is a key issue. As the VLSI feature size scaling down and meanwhile operating frequency increasing, the modeling work becomes more difficult than ever for high-performance digital ICs. Nevertheless, most conventional techniques of gate modeling are based on the switch-resistor model;(i.e., a voltage source concatenating a driving resistance), which can only capture the gate characteristic in its switching region. Hence, these modeling techniques have to decouple the gate with its interconnects and compute a piecewise linear function for the driving source in the iterative computation of effective capacitance [1, 3, 4]. Since the driving source of the model is dependent on gate load, when the design modification affects the load, the gate has to be modeled again almost from the beginning for a new timing analysis. The efficiency will be deteriorated in synthesis loops due to this. In this paper, we present an explicit gate delay model, which is not sensitive to gate load and can be pre-computed before timing analysis and synthesis. Thus, the repetition of modeling work is totally unnecessary even when the gate load keeps on changing in the performance optimization procedure. The efficiency is certainly improved in the synthesis/optimization loops. The advantage is attributed to using a second-order circuit as the model base. This two-pole approach also certifies the model to yield an accurate result to match the non-linear output of gate.

As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. For a uniform width metal interconnect, the current flows through the driving point is much larger than that flows through the fan-out point since much of current bypasses to the ground through the parasitic capacitance. This causes the lifetime of driving point to be quite shorter than that of fan-out point due to electromigration. In order to avoid breakdown at the driving point, wire sizing is an effective solution. Thus we present a wire shape, of which the current density as well as the lifetime is uniform along the wire. SPICE simulation results show the uniformity of current density of this wire shape. Under the same current density bound, we demonstrate that chip area and power consumption are significantly reduced for this wire shape compared to the uniform width wire. The wire shape functions we derived are continuous. However, it is not necessary to ultra-accurately reproduce the continuous shape on the silicon, since we can round the continuous shape to the nearest available litho width and this will not degrade the uniformity of current density.

In this paper, we propose a statistical technique for detecting and eliminating initial transient in power analysis. While most power analysis approaches are based on the assumption of stationarity, artificial nonstationarity, or initial transient, may be introduced in early simulation period due to improper initialization. Left unattended, initial transient can seriously undermine the power estimation accuracy. As a remedy, we devise a statistical test for nonstationarity detection based on the Brownian bridge, the asymptotic behavior of a power dissipation sequence. Using the test, a stopping criterion is designed to determine if the circuit is warmed up enough for normal power analysis to proceed. The experimental results show the proposed technique efficiently detects and eliminates initial transients, thus maintaining power estimation accuracy.

This paper presents a new method for determining the widths of the power and ground routes in integrated circuits so that the area required by the routes is minimized subject to the reliability constraints. The basic idea is to transform the resulting constrained nonlinear programming problem into a sequence of linear programs. Theoretically, we show that the sequence of linear programs always converges to the optimum solution of the relaxed convex problem. Experimental results demonstrate that the sequence-of-linear-programming method is orders of magnitude faster than the best-known method based on conjugate gradients, with constantly better optimization solutions.

In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. The present parametric statistical technique estimates the average power based on the assumption that the power distribution can be characterized by a preassumed function. Large error can incur when the assumption is not met. On the other hand, the existing nonparametric technique, although accurate, is too conservative and requires a large sample size in order to achieve convergence. For a good tradeoff between simulation accuracy and computational efficiency, we propose a new nonparametric technique using the properties of the order statistics. It is generally applicable to any type of circuit irrespective of its power distribution function. Compared to the existing nonparametric technique, it is much more computationally efficient since it requires a much smaller sample size to achieve the same accuracy specification. This new technique is implemented in the distribution-independent power estimation tool (DIPE). DIPE is empirically demonstrated to be more robust and accurate than the parametric technique.

In this paper, we present a new statistical techniquefor estimating average power dissipation in sequential circuits.Due to the feedback mechanism, in sequential circuitspower dissipation in consecutive clock cycles are temporallycorrelated, which violates the basic requirement ofstatistical mean inference procedures. We overcome thisproblem by using a randomness test and a sequential procedureto select a proper independence interval, which in turnis used to generate random power samples. A distribution-independentstopping criterion is applied to analyze thesample data and terminate the simulation upon achievementof the accuracy specification. The technique is successfullyapplied to a set of benchmark circuits.

A new statistical technique for average power estima-tion in sequential circuits is presented. Due to the feed-back mechanism, conventional statistical procedures cannot be applied to infer the average power of sequential circuits. As a remedy, we propose a sequential procedure to deter-mine an independence interval which is used to generate an independent and identically distributed (iid) power sam-ple. A distribution-independent stopping criterion is applied to choose an appropriate convergent sample size. The pro-posed technique is applied to a set of sequential benchmark circuits and demonstrates high accuracy and efficiency. I.

We present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power based on the assumption that the power distribution can be characterized by a preassumed function. A large error can result if the assumption is not met. To overcome this problem, we propose a nonparametric technique in which no distribution function needs to be assumed. A set of distribution-independent upper and lower bounds of the average power are developed using the properties derived from the order statistics. A stopping criterion is designed based on the bounds for a desired percentage error with a specified confidence level. Since it does not resort to assuming any particular distribution function, the technique can be applied to all circuits irrespective of their power distributions. Comparison is made against the present statistical technique based on the central limit theorem. Experimental results show that the proposed technique is much more accurate and robust, yet the efficiency characteristic of statistical techniques is still preserved.