This paper deals with the power allocation problem for coded multicarrier transmission. Specifically, we focus on a bit interleaved coded modulation (BICM) packet transmission implemented with orthogonal frequency division multiplexing (OFDM) and in the presence of automatic repeat request (ARQ) protocol. Capitalizing on the binary-input output-symmetric (BIOS) nature of the BICM channel it is provided a simple upper-bound of the rate of information bits received without any error, the so called goodput. Based on this theoretical characterization, we develop a power allocation strategy among the different subcarriers so that the system goodput performance metric is maximized. The effectiveness of the proposed method is numerically testified for BICM-OFDM transmission in the context of the typical WLAN scenario.

This paper deals with channel estimation in ultra-wideband communications operating in a multipath environment and in the presence of multiaccess interference. The channel parameters are the attenuations and delays incurred by the signal echoes along the propagation paths. Time-hopping modulation with binary symbols is assumed. The estimation method is based on the maximum-likelihood criterion and is applied to two different scenarios: either with known symbols (DA estimation) or with unknown symbols (NDA estimation). The effects of the estimation errors on the performance of a RAKE receiver are assessed by simulation by comparing the receiver bit-error rate with either perfect channel estimates or imperfect estimates as obtained from the proposed algorithms. The results show that the degradations are tolerable as long as the number of users is limited. They also show that the DA method has an edge over the NDA in that it can handle a larger number of users for a fixed degradation. The number of users that can be accommodated in practice is found for some values of the system parameters.

This paper deals with the analysis and design of efficient non-data-aided clock and carrier (frequency/phase) synchronization algorithms intended for use in satellite digital video broadcasting systems employing turbo-coding techniques to enhance the power efficiency. The above issue appears quite challenging in view of both the extremely low signal-to-noise ratio, typical of turbo-codes operation, and the very short time allocated to the acquisition of synchronization parameters. These constraints rule out most conventional clock/carrier recovery schemes and demand a careful search for specific, highly efficient algorithms. We propose and analyze a clock/carrier synchronization scheme capable of operating at values of E/sub b//N/sub o/ as low as 1 dB with lock-in delay not exceeding 50 ms.

The linearization technique known as amplitude and phase (A&P) predistortion, proposed by D'Andrea and Lottici, is applied to the orthogonal frequency-division multiplexing (OFDM) transmission context with nonlinear radio-frequency high-power amplification. The above technique is shown to provide a major enhancement in power efficiency in comparison with the unprotected system, as well as a nonnegligible gain over an alternative linearization strategy, identified as minimum mean-square-error (MMSE) predistortion, presented in the literature for application to OFDM. The relative performance of the A&P and the MMSE predistorter schemes is assessed over the additive white Gaussian noise channel and also in a frequency-selective fading environment. The impact of adjacent channel interference is also discussed.

The linearization technique known as amplitude and phase (A&P) predistortion, proposed by D'Andea et al. (1996), is applied to the OFDM transmission context with nonlinear RF high-power amplification. The above technique is shown to provide a major enhancement in power efficiency in comparison with the unprotected system, as well as a nonnegligible gain over an alternative linearization strategy, identified as minimum mean square error (MMSE) predistortion, presented by Di Benedetto and Mandarini (1995) for application to OFDM (Benedetto and Mandarino 1996). The relative performance of the A&P and the MMSE PD schemes is assessed over the AWGN channel and also in a frequency-selective fading environment.

This paper describes an effective technique for the optimization of the clock recovery circuit in an all-digital modem for linearly modulated signals. Starting from the concept of prefiltering of the data signal (already pursued by these authors in the context of analog data receivers), it is shown how to design an optimum digital prefilter for the minimization of jitter due to both Gaussian and pattern noise in the closed-loop clock recovery scheme by Gardner (1986). The numerical results of the theoretical analysis, obtained after iterative resolution of a constrained-minimum problem via the Lagrange multiplier method, are checked by simulation and can be nicely justified by the consideration of the frequency response of the optimum prefilter. The key outcome of such an approach is the demonstration of a substantial performance improvement in terms of steady-state clock jitter, even with remarkably simple FIR prefilters with a small number of taps.

This paper presents a novel technique for power amplifier linearization in digital microwave radio systems. The proposed technique is based on the use of a predistortion circuit, whose AM/AM and AM/PM responses are separately implemented as polynomial approximations of the respective responses of the ideal linearizer. The proposed scheme is shown to attain superior performance in comparison with other well-known predistortion structures, such as those based on the cancellation of third or fifth order distortion, with no substantial aggravation in implementation complexity.

Symbol timing in continuous phase modulated signals is investigated making use of maximum likelihood estimation methods. Nondata-aided algorithms are proposed with a feedforward structure. They are suitable for digital implementation and can be employed with either full or partial response signaling. Multilevel symbol alphabets are allowed and the modulation index may be arbitrary. The performance is assessed by analysis and simulation. It turns out that full response schemes are comparatively easier to synchronize. Difficulties arise with partial response signaling especially with long frequency pulses.

Frequency tracking loops are used in digital links to control the carrier frequency of the received signals. A basic component in such loops is the frequency difference detector (FDD). This paper concentrates on a class of FDDs for use with binary continuous-phase modulation (CPM). Their derivation is based on two ideas: the maximum-likelihood principle for parameter estimation and Laurent's (1986) decomposition of a CPM signal into the sum of linearly modulated components. The proposed FDDs are suitable for digital implementation and their operation is independent of clock recovery. Analysis and simulation are employed to investigate tracking operation and acquisition capability of frequency control loops endowed with such FDDs. Numerical examples are provided for modulation schemes of practical interest such as MSK and Gaussian MSK. The loop acquisition range is found to be fairly large, about 0.5-1.0 times the bit rate.>

This paper describes a design method for the synthesis of digital filters in data communication systems. The coefficients in the transmit and receive filters are optimized to meet specified requirements on (i) out-of-band emission, (ii) intersymbol interference, (iii) adjacent channel interference and (iv) thermal noise immunity.>

Frequency tracking loops are used in digital links to control the carrier frequency of the received signals. A basic component in these loops is the frequency difference detector. This paper concentrates on two detectors that have previously been derived from maximum likelihood estimation criteria. Noise spectra of the detector outputs are computed and the results are used to assess the performance of frequency control loops operating in the tracking mode. Computer simulations are used to validate the theory. The detector implementation in digital form is also addressed and design criteria are provided that lead to structures with a limited computing complexity. Comparisons are made with other frequency detection schemes available in literature.>

We introduce the modified Cramer-Rao bound (CRB) which, like the true CRB, is a lower bound to the error variance of any parameter estimator. The modified CRB proves useful when, in addition to the parameter to be estimated, the observed data also depend on other unwanted parameters. The relationship between the modified and true CRB is established and applications are discussed regarding the estimation of carrier-frequency offset, carrier phase, and timing epoch in linearly modulated signals. Modified CRBs for phase and timing estimation have been already discussed in previous works where it is shown that several practical carrier-phase and clock recovery circuits do attain such bounds. Frequency discrimination, instead, is not so well-represented in the literature and a significant contribution of this paper is the calculation of the modified CRB for frequency estimation. This bound is compared with the performance of some frequency detectors and it is concluded that further work is needed in search of more efficient frequency discrimination methods.>

An approximate method is discussed for maximum likelihood estimation of coded PSK sequences in the presence of an unknown carrier phase. This method makes use of the Viterbi algorithm to find an optimum path in the encoder trellis diagram. Phase estimation is embedded into the structure of the detection algorithm and the branch metrics in the trellis are modified with respect to those employed with known carrier phase. Comparisons with traditional decoding schemes show that the proposed solution has better performance in terms of acquisition time and cycle slips.>

Performance of the digital clock recovery scheme proposed by F.M. Gardner (1986), when applied to quadrature-amplitude-modulation (QAM) microwave radio communication systems is investigated. In particular, it is shown how to improve such a scheme by means of appropriate prefiltering of the incoming signal. The impulse response of the shaping filter is designed to achieve pattern-jitter-free clock recovery in the case of an ideal transmission channel. The impact of multipath fading on synchronizer performance is evaluated by means of computer simulation.>

The authors investigate the performance of an automatic frequency control loop operating in a receiver for linearly modulated digital signals. The loop uses a balanced quadricorrelator as a frequency detector. The design of such a detector for optimum loop tracing performance is considered. This problem involves the analysis of the disturbances generated in the quadricorrelator, which are conveniently divided into self-noise and thermal-noise-induced components. It is shown that the quadricorrelator can be designed to make self-noise negligible in the steady state, both with staggered and nonstaggered modulations. This leaves the thermal-noise-induced components as the sole obstacle to loop operation in the tracking mode. The level of such components is then minimized by further selection of the quadricorrelator filters. Numerical examples are worked out to assess the advantages of optimized quadricorrelators over more conventional schemes. It is found that tracking errors can be substantially reduced with no penalty for frequency acquisition times of the loop.>

A theoretical evaluation is presented of the mean time to first slip for some closed-loop synchronizer schemes to be used in a coherent serial receiver for offset binary modulations. Various modulation formats belonging to this class are considered, and the mean time to first slip is computed for each modulation type for different values of loop bandwidth and signal-to-noise ratio. Theoretical results are confirmed by extensive computer simulations.>

An analysis is presented of a balanced quadricorrelator driven by a digital-modulated signal with thermal noise. The aim is to assess its performance as a frequency difference detector. The circuit output is decomposed into a signal term and a disturbance referred to as noise. Exprssions are given for the signal and for the power spectral density of the noise as a function of the various system parameters. Design criteria are provided to minimize the output noise for zero frequency offset. In particular, it is found that at high signal-to-noise ratios the noise level can be made vanishingly small by the proper choice of the quadricorrelator filters. A similar result has been recently discovered for another frequency difference detector, the dual-filter detector. It is shown that a balanced quadricorrelator and a dual-filter detector can be made totally equivalent.>

This paper presents an analysis of a synchronization circuit to be used for carrier-phase and symbol-timing recovery in continuous phase modulation systems.M-ary modulation formats with arbitrary pulse shaping and rational modulation indexes are assumed. Circuit performance is expressed in terms of variances of phase and timing errors. Numerical results are provided for some important cases, including minimum shift keying and tamed frequency modulation. Theoretical results are found in good agreement with computer simulations.

A general analysis is provided for the jitter performance of a delay clock regenerator as a function of various system parameters such as modulation format, channel filtering, signal-to-noise ratio, and line delay. The novelty with respect to previous works on the same subject is that we find an expression for the jitter variance of the regenerated clock, while other studies have dealt with an upper bound to such variance. Numerical results have been checked by computer simulations.

Previous authors have found that jitter-free operation is achievable with appropriate pulse shaping when the nonlinearity in the timing recovery circuit is a square-law rectifier. In this paper we consider the general case of an arbitrary nonlinearity and we show that a class of pulses can still be found which provide very good jitter performance. Comparisons are made with previous results.

Computer simulation is employed to assess jitter performance of a clock recovery circuit as a function of the characteristics of the rectifier being used. Several types of rectifiers are compared, some operating at baseband, others at intermediate frequency (IF). It is shown that the best choice between them depends both on the modulation format and on the excess bandwidth factor of the pulse spectrum. In QPSK systems, fourth-law rectifiers outperform the others for rolloff factors up to 0.2 while, for higher values, baseband absolutevalue rectifiers are preferable. In the case of 9QPRS, baseband absolutevalue rectifiers provide jitter reductions of one order of magnitude at high signal-to-noise ratios.

In this paper we analyze the synchronization properties of a digital loop conceived for PSK carrier recovery. The effects of a frequency step and additive Gaussian noise are evaluated by means of the Markov chain technique.

A first-order nonuniform multilevel quantized DPLL is analyzed in the presence of a phase- and frequency-step signal plus Gaussian noise. The system is modeled as a homogeneous finite Markov chain. In this way, closed-form expressions are obtained for the steady-state probabilities, the mean and rms values of the phase error, and the mean number of samplings to slip a cycle or to reach acquisition. Numerical results are also presented.

A non-uniform sampling digital phase locked loop (DPLL), with a hard limiter as quantizer, is analyzed by a graphical method in the case of phase and frequency step inputs and no noise. The cycle slipping and the limit cycles phenomena are investigated. An upper-bound to the model gain and, consequently, to the pull-in range is obtained. Also a closed-form expression of acquisition time is derived. Moreover, using a random-walk model, the stationary phase error variance, the mean acquisition time and the mean first slip time have been evaluated. Some two channel configurations are proposed, which allow us to obtain a faster acquisition. Finally the problems relevant to the practical implementation of the loop are analyzed.