An integrated BCD gate driver employing adaptive dead-time control (ADTC) and a compact gate-boost (GB) circuit is presented. The ADTC reduces both dead-time intervals from conventional$\sim 10 ~\text{ns}$to a nearly load-independent high-to-low dead time$\left(D T_{F}\right)$of$0.7-1.2 ~\text{ns}$over$1-6 ~\mathrm{A}$, and digitally minimizes low-to-high dead time ($D T_{R}$) to$\sim 1 ~\text{ns}$, lowering bodydiode conduction and reverse-recovery losses. At$38 ~\mathrm{V}, 6 ~\mathrm{A}$, and 2.2 MHz, this recovers a combined dead-time loss of up to 1.47 W, yielding an efficiency gain of 1.81 %. In addition, the open-loop GB circuit accelerates the later stage of the high-side transition, halving the$L X$rise time (28.4 ns to 14.5 ns) and yielding an additional 1.09 W loss reduction and 1.33 % efficiency gain. Overall, the proposed solution achieves a total loss reduction of 2.56 W and a 3.14 % absolute efficiency improvement.

This paper proposes the first simultaneous wireless power and data transfer (SWPDT) integrated circuit (IC) which exploits a Capacitive-Inductive Channel (CI-Channel), enabling concurrent power and data transmission. The communication across the CI-Channel can support data-only transmission or can be incorporated into the system control loop, allowing output voltage regulation through phase-shift control applied at the primary side. The proposed IC can be configured as primary side (power transmitter, P-TX, and data receiver, RX) or secondary side (power receiver, P-RX, and data transmitter, TX). In order to ensure communication robustness, unwanted disturbances are removed through specifically designed Power Blanking and Ringing Blanking circuits. The proposed SWPDT IC test-chip prototype was fabricated using a 130-nm BCD process and experimentally verified considering the complete wireless power transfer (WPT) system, including primary side, CI-Channel and secondary side. The overall system, targeting medium-power industrial applications, achieves a maximum 5.3-W output power, a peak efficiency of 83.7% and a load regulation of 0.09 mV/mA. Moreover, a 540 kb/s data rate with no transmission errors across$10^{9}$bit acquisitions, corresponding to a bit-error-rate (BER)$\lt 10^{-9}$, was achieved.

A high-speed, low-figure-of-merit capacitive floating level shifter (CF-LS) for high-side bootstrapped gate drivers is presented. The design integrates a feedback discharge control (FBDC) for enhanced$V {_{\text {SW}}}$dV/dt (SRSW) immunity and combines a mismatch reduction circuit (MMRC) with a common-mode blanking pulse (CMBP) to block common-mode (CM) signals with mismatch. Fabricated in a 0.75-$\mu $m STMicroelectronics bipolar-CMOS-DMOS (BCD) process, the proposed CF-LS occupies 0.048 mm2with the core area being 0.026 mm2, making it highly compact and integration-friendly. It achieves a propagation delay ($T {_{\text {P}}}$) of 1.525 ns and transition energy ($E_{T}$) of 29.77 pJ at 40 V, both of which remain approximately constant across the$V {_{\text {SW}}}$sweep from 0 to 40 V, while maintaining measured SRSWimmunity of up to 20 V/ns and mismatch tolerance up to 30%. Compared to recent works, the design offers a$2\times $improvement in figure-of-merit2 (FoM2), achieving 2.68 ns$\cdot $pJ/$\mu $m${^{{3}}} \cdot $V at bootstrap supply ($V {_{\text {BS}}}$) of 5 V, and$3\times $improvement when supplied at 3.3 V. The CF-LS has been comprehensively validated both as a standalone circuit and when integrated within a dc–dc buck converter, making it a highly robust, efficient, and versatile solution for high-frequency power management systems operating up to 55 MHz.

This paper introduces a dynamic current comparator employing a parasitic charge recycling technique to achieve an ultra-low energy per comparison of 175 fJ. Furthermore, incorporating a switched capacitor supply in the static portion of the circuit, the comparison energy is further reduced to 55 fJ, more than three times lower. The proposed circuit, designed and extensively simulated in a 130-nm CMOS process with thick gate MOS transistors, demonstrates a comparison time of 3.8 ns, with a 100-nA input difference and a 32-MHz clock, while offering an input-referred noise of 2.9 nArms. These features make the proposed comparator highly suitable for medium-to high-resolution data conversion systems, particularly in biomedical and sensor-readout applications. Additionally, it is well-suited for high-speed and cryogenic CMOS systems, where current-mode architectures are becoming increasingly relevant.

A 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm CMOS is presented. Designed for the readout of inertial sensors in micro-electromechanical systems (MEMS) technology, it combines an asynchronous control scheme with a 2-bit per cycle architecture achieving enhanced energy efficiency. Operating at a 1-MS/s sampling rate, the proposed ADC draws 8.9-µA of total current from a 1.8-V supply. Additionally, it demonstrates an SNDR of 63.2 dB across the entire Nyquist bandwidth, resulting in a Walden figure-of-merit (FoM) of 13.6 fJ/conv-step. The achieved energy efficiency makes the proposed ADC suitable for battery-powered applications requiring medium resolution and data rate.

High-performance linear LED drivers for RGB applications rely on an accurate current generation to achieve the desired luminous intensity or color accuracy. Random hardware faults are a class of malfunctions that can occur during the lifetime of a device, like for example: a bonding failure, an excessive device aging leading to large MOS threshold drift, gate-oxide shorts, etc. For LED drivers, random faults are detected by monitoring the output current. The random fault coverage (RFC), i. e. the percentage of random faults that can be detected by the hardware dedicated to the monitoring function, can be surprisingly low if the current monitor is not specifically designed for this goal. This paper presents a novel current monitor, based on a cascode structure as a sensing element and fabricated in a conventional 180-nm CMOS process, capable of achieving an RFC of 90%. This remarkable result is obtained with an area overhead of only 8.5% with respect to a conventional approach.

This paper presents a Current-to-Digital Converter (CDC) designed for Computed Tomography (CT). The circuit, featuring a fully differential architecture, has been fabricated in a 0.35-µm-CMOS technology with a silicon area of 0.65 mm2and consumes 300 nJ per conversion from a nominal supply voltage of 3.3 V, with a conversion period of 200 µs. The average power consumption is reduced by 22% by applying a dynamic power consumption scaling technique based on operational amplifier slicing. The proposed CDC achieves a dynamic range of 89 dB (12.75 ENOB) over a 2.5 kHz bandwidth, leading to a Schreier figure-of-merit of 151.2 dB.

This paper proposes a three-stage operational transconductance amplifier (OTA) with slew-rate enhancing, especially designed for interfacing triboelectric nanogenerator sensors in smart textile applications. The proposed OTA, designed in a 130-nm BCD process, features 0.015-mm2area and 2.7-µW power consumption with 1.3-V supply voltage, while meeting the specifications of the targeted application, thus constituting a very compact low-power low-voltage solution. The proposed OTA was extensively simulated with Cadence Virtuoso, verifying its post-layout performance and robustness against process, voltage and temperature (PVT) variations.

A high-speed low-figure-of-merit capacitive-coupled level shifter tailored for high-side bootstrapped gate drivers is presented. Key techniques include a Feedback Discharge Control (FBDC) for improved dV/dt Immunity, a MisMatch Reduction Circuit (MMRC) in combination with Common-Mode Blanking Pulse (CMBP) to block common-mode signals with improved mismatch tolerance. The level shifter is fabricated in a 0.75µm STMicroelectronics BCD process and covers a chip area of 0.048mm2. Experimental results demonstrate a Propagation delay (TP) of 1.525ns and Transition Energy (ET) of 29.77pJ at 40V, with a dV/dt immunity of up to 20V/ns. The level shifter achieves a figure-of-merit 2 (FoM2) of 2.68ns.pJ/um3.V, an improvement of 2x from the recent literature, and exhibits a mismatch tolerance of 20%. The design has been tested at a switching frequency (FSW) of up to 55MHz. The design is validated through standalone and integrated testing in a DC-DC buck converter.

This paper focuses on control techniques for an integrated Dual Active Bridge (DAB) converter designed for low-voltage (5V) and low-power (2W) applications. The analysis concentrates on the single-phase-shift (SPS) modulation, as it offers the best balance between implementation simplicity and power efficiency for a control loop circuit that must be embedded within the system. Moreover, an innovative modulation technique called controlled single-phase-shift (CSPS) is introduced, which dynamically adjusts the phase-shift to maximize current flow through the load. This approach enhances the output power range by 33%, achieving an increase in the average efficiency throughout the phase-shift interval up to 4% when compared to the conventional SPS modulation. Circuit-level simulations have been conducted in Cadence Virtuoso environment to verify the effectiveness of the proposed approach.

This paper introduces a quasi-passive Noise-Shaping Successive Approximation Register Analog-to-Digital converter (NS-SAR ADC) suited for low power Audio Activity Detection (AAD). Exploiting a 2ndorder Error-Feedback (EF) loop filter implemented through a low power open loop amplifier, insensitive to Process-Voltage-Temperature (PVT) variations, and a fully passive Charge-Sharing (CS) summing node, this converter reaches 78 dB of Dynamic Range (DR), achieving a Schreier Figure-of-Merit (FoMs) of 165.3 dB. Fabricated in a 65-nm BCD process, the proposed ADC core occupies 0.129 µm2consuming 14.9 µW from a 1.2-V supply.

This paper presents a monolithic GaN current sense circuit designed for the high-side of a 100-V half-bridge. The circuit is engineered to minimize current offsets and response times across a wide range of input voltages (10 V to 100 V), as well as varying temperatures and current loads. It is capable of tracking inductor current ripples and detecting the zero-current condition of the half-bridge high-side power transistor. The proposed solution demonstrates a simulated loop gain exceeding 100 dB and a bandwidth of 43.9 MHz, which achieves an accuracy of 99.4% and a response time of 145 ns under operating conditions of 50-V input voltage, 10-A current load, and 27°C.

This paper focuses on the impact of segmentation on the linearity performance of gigasample rate current-steering digital-to-analog converters (DACs). The effect of their output impedance drop and code-dependency occurring at increasingly higher data rates is studied with the purpose of deriving relevant design constraints about the segmentation scheme choice. This analysis is supported by extensive simulation results carried out with special attention to the spurious-free-dynamic-range (SFDR) and third-order-intermodulation-distortion (IM3) metrics. Lastly, a 10-bit 6.4 GS/s DAC designed in a 55-nm BiCMOS technology is presented and discussed in relation to the previously determined scenarios. Besides featuring a 65.9-dBc SFDR at 1 GHz and an IM32.

This paper presents the system-level discussion, simulation design, and fabrication results of a novel analog ASIC - fabricated in 130nm BiCMOS technology - for interfacing resistive thermal sensors known as Fly Height Sensors (FHSs). FHSs are attached to the magnetic recording heads in modern hard disk drives (HDDs) to monitor the head-disk distance known as “fly height” by measuring the FHS resistance variation. The magnitude of the sensor signal serves as a measure of the proximity between the head and the disk surface which must accurately be controlled to minimize the fly height, thereby increasing the storage capacity of HDDs. The proposed interface includes two parts: 1) a dual-mode precise bias circuit that accurately provides a differential bias with a programmable common-mode voltage to the FHS in both voltage (V) and current (I) modes without requiring any calibrations, as well as featuring fast and smooth transient response, 2) front-end gain stages that create two separate signal paths with low- and high-frequency responses, called LF and HF blocks, utilized for controlling the fly height and mapping the roughness of the disk surface, respectively. The proposed bias circuit demonstrates high-impedance loading behavior on the sensor terminals in both V- and I- modes to have a unity signal gain at the sensor port and deliver it to the front-end amplifiers, resulting in an improvement of the overall noise performance of the interface. In addition, the bias noise power at the output of the LF block is suppressed to the extent of one order of magnitude thanks to deploying a noise cancellation technique. A low-noise and wide-bandwidth front-end is implemented for the HF block that eliminates the need for configuring the bias loop for having a low cutoff frequency, resulting in a reliable design with reduced complexity. Additionally, degenerated differential pairs with resistive loads, split tail currents, and Caprio’s quad offering low gain variation over the temperature and process are implemented as the front-end gain stages. The fabricated chip features an active area of 1.28 mm2with power consumption in the range of 110 to$172~mW$for the V-mode and 78 to$107~mW$for the I-mode, considering typical supply voltages of$+3.3\; V$and$-2.6 \;V$, and the sensor resistance ($R_{SNS} = 75\; \Omega $) and the sensor current ($I_{SNS}$) from 0.5 to$6\;mA$.

This paper presents a Class-D audio amplifier, fully compatible with standard BCD technologies, that features in the direct signal path an ADC ($\Sigma\Delta$modulator), a digital third-order loop-filter and digital PWM. The overall closed-loop mixed-signal architecture pushes most of the signal processing towards the digital domain, thus allowing the use of scaled technologies to reduce cost and size. Moreover, the high gain developed by the digital filter and by the integrator inside the$\Sigma\Delta$modulator, attenuates the residual high frequency ripple around the loop and concurrently improves the THD+N in the audio band. In this paper the feedback is closed after the output LC filter, thus mitigating the influence of its components on the amplifier transfer function and on the linearity. The proposed architecture achieves in simulation 120 dB of SNR and a THD of 0.01%-0.001 %, even in wide input signal conditions.

This paper presents a novel capacitive-inductive structure implementing the channel for power and data transmission in a wireless power transfer system. The structure consists of two$24-\mu\mathrm{H}$coil inductors, each surrounded with an open ring copper layer realized on a printed circuit board (PCB). The proposed channel structure allows simultaneous transmission of power and data: indeed power is transferred through the magnetic field generated by the coils, while data are modulated and transferred through the electric field produced by the capacitance determined by the copper rings and the parasitic capacitance of the two coils. The proposed structure was extensively studied and characterized both through simulations and measurements: compared to the state-of-the-art, in which metal plates placed below the coils are employed for implementing the capacitance used for data transmission, it shows a significant decrease in parasitic capacitance between the copper ring and the coil, thus reducing power disturbances on the data transmission.

This paper proposes a time-domain-based architecture for implementing a bandgap reference: indeed, the proportional-to-absolute-temperature (PTAT) voltage is provided by subtracting the gate-to-source voltages ($V_{GS}$) generated in two subsequent phases by the same diode-connected NMOS device, operating in subthreshold region and biased at different currents. As the same transistor is employed in both phases for the PTAT voltage generation, mismatch effects are inherently reduced. The proposed bandgap reference combines the PTAT and the complementary-to-absolute-temperature (CTAT) voltages by means of a switched capacitor difference amplifier and, if required, includes a dedicated sampling and filtering circuit. It features 5-bits trimming and implements curvature compensation through the addition of an integrated resistor with appropriate temperature dependence to the CTAT branch. The proposed bandgap reference circuit was designed in a standard 130-nm CMOS process and was extensively simulated in Cadence Virtuoso, achieving a worst-case 0.756-ppm/°C temperature coefficient.

This paper presents a SAR-assisted first order incremental$\Sigma\Delta$analog-to-digital converter (ADC) equipped with an accumulation based sample and hold (S/H) circuit to effectively limit its kT/C noise contribution, potential bottleneck for the resolution performance of the converter. This system has been designed for shunt current measurements in the electrical drives battery management framework; the sensed and digitized current information is needed for a proper monitoring and regulation of the behaviour of these essential devices for automotive applications. The converter has been developed at the behavioural level in the MATLAB Simulink environment with special attention to the S/H circuit which has been analyzed in Cadence Virtuoso; the complete system features a high common mode voltage (HCMV) in the order of tens of Volts, a peak-to-peak 50 mV differential input range and a target resolution of 12 bits.

This paper presents a trimming technique to suppress the thermal effects of process spread of BJT-based temperature processing circuits. The proposed calibration method has the advantage of requiring a reading at a single temperature while compensating for the spread of the thermal behaviour of the base-to-emitter voltage of bipolar transistors; in addition to this, the effectiveness of the proposed technique is improved by an exponential approach carried out on the design of the trimming structure. The strength of the presented technique is shown to be effective on a 6-bit trimming circuit designed and extensively simulated in a standard 180-nm CMOS process; this implementation provides a reduction of the considered spread of about 90% making it suitable for a number of applications in which process variations limit the accuracy of the circuit.

This paper presents a novel micromachined high-responsivity thermopile sensor, fully compatible with standard CMOS-SOI (Silicon-On-Insulator) processes. The proposed thermopile features a versatile mosaic structure, based on 128 60 μ m × 60 μ m pixels connected in series and/or in parallel. Two versions of the proposed thermopile sensor, featuring a different number of equivalent pixels, are presented and fully characterized. The most performing of the two features $2.9\cdot 10^{4}\frac{V}{W}$-responsivity, outperforming other state-of-the-art thermopile sensors. The application of the most performing thermopile as proximity and motion detector was also verified through measurements.

A 12-bit low-power SAR ADC with low-input capacitance is proposed. The topology exploits a structure with separate sample & hold and DAC blocks, separated block SAR, to achieve low-input capacitance. In this structure, the comparator input common-mode voltage is variable and, therefore, a rail-to-rail comparator with rail-to-rail offset cancellation is proposed to cancel the input common-mode dependent offset. The proposed comparator is modified to overcome the uneven distribution of kickback noise too. In order to achieve a 12-bit resolution, the bootstrapped switch is modified. With the aid of the proposed offset cancellation, kickback noise reduction, and switch, the ADC achieves 11.08-bit ENOB and the input capacitance is reduced to 2 pF, leading to relatively low input power consumption with no need for a reference supply voltage.

This paper presents a microsystem suitable for contact-less human body temperature measurements, as well as for presence, motion and proximity detection. It consists of a 130-nm CMOS-SOI MEMS (Micro-Electro Mechanical System) thermal sensor, referred to as “TMOS”, and its 130-nm CMOS interface circuit. The TMOS, based on a micromachined transistor, being an active device, features advantages in terms of internal gain: with optimal biasing, indeed, the TMOS achieves 274-$\mu \text{V}/^\circ \text{C}$input-referred sensitivity at 3-cm distance and 50.33° field-of-view (FOV), outperforming thermopile detectors. The sensor and the interface circuit, featuring a chopper-stabilized-based analog readout with a 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter), were mounted in the same package and extensively measured: the microsystem achieves repeatability and ±0.17°C precision, thus satisfying the requirements for contact-less human body temperature measurements; furthermore, its performance as presence, motion and proximity detector was also verified.

This paper presents a readout circuit for thermopile-based thermal sensors, suitable for contactless temperature measurements. The circuit, designed and extensively simulated in a standard 130-nm CMOS process, employs chopper stabilization in order to minimize offset and noise contributions at low frequency, while providing proper amplification to the input signal, which behaves substantially as a DC. The circuit nominal supply voltage is 1.2 V and its power consumption is approximately 260 μW. The proposed single-ended architecture solves the drawbacks of the most straightforward fully differential approach, while achieving a simulated input-referred residual offset mean value equal to 84.4 nV, with 487 nV of standard deviation. An accuracy of ±0.3°C is provided at room temperature, making the circuit suitable for medical devices, such as contactless fever thermometers, and security systems, such as motion and human presence detection sensors.

In this paper we present a monolithic microsystem, which can perform Bio-Impedance Analysis (BIA), and electro impedance tomography (EIT) measurements as well as record electrocardiogram (ECG) signals. In contrast to a full analog lock-in approach, a mixed analog/digital solution is adopted. The proposed solution has been designed, implemented and tested using a commercial 0.35-μm CMOS technology. The tuning range of the signal generator and the detector is from 10kHz to 10MHz in 1kHz steps. The circuit ensures a CMRR of 81dB@10kHz, which increases to 84dB@10MHz. The measured equivalent input noise power spectral density is en=2.57nV/√Hz at 10kHz in the worst case, close to the 1/f corner frequency. It decreases until en=1.8nV/VHz at 1MHz and en=1.9nV/√Hz at 10MHz. Measurements of a reference RC network performed with the proposed monolithic solution and compared with a Keysight E4980A Precision LCR Meter shows a maximal relative error of 0.8% over the whole operating frequency range.

In this work a high-resolution, low power, successive approximation register (SAR) ADC for X and Gamma Ray Silicon Drift Detector read-out in space applications is presented. The proposed scheme, implemented at transistor level in 0.35 μm CMOS technology consists in an input buffer, a high resolution comparator, a logic control circuit and a capacitive DAC. Simulations carried out in worst case matching between the capacitance elements and by considering intra and inter-die variations show an effective number of bits equal to 11.97 and a SNDR of 73.8 dB. The simulated DNL performance is -0.1 ÷ +0.1 LSB while the INL is equal to -0.14 ÷ + 0.14. The mean power consumption is 0.27 mW while the ADC FoM is only 87 fJ/step.

This paper presents an FSK modulator suitable for a transmitter chain within the new USB Power Delivery standard. The proposed solution performs a binary FSK modulation using a relaxation voltage-controlled oscillator with a voltage averaging feedback. A reference proportional to supply is used to compensate real-time frequency variations, whereas the frequency spread due to the process is corrected by an 8 bit trimming system. The considered input signal bit rate is 300 kbps and the carrier frequency is 23.2 MHz with ±0.5 MHz frequency deviation. The proposed modulator grants ±0.9% accuracy against PVT spread by consuming 1.2 mW and phase noise at 20kHz from the carrier lower than -56 dBc/Hz.

In this paper a low-cost integrated wide-range gas sensor interface based on a resistance-to-time converter is presented. The circuit in transistor level simulation achieves a linearity better than 0.5% over a range of 6 decades i. e. 1 kΩ ÷ 1 GΩ, without requiring any calibration or auto-ranging. The maximum sensing time is 0.5 s, while measuring the highest resistance value. The state-of-the-art of this measurement has been improved by extending the acceptable input resistance range, while lowering the maximum power consumption. More over, a very high linearity has been achieved by canceling the parasitic effects of the multiplexer addressing the sensor matrix.

In this paper we present a MASH bandpass ΣΔ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each ΣΔ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The ΣΔ modulator is implemented using a 0.18-nm CMOS technology and a sampling frequency of 180 MHz. The simulations at transistor level show a resolution of about 13 bits, with a bandwidth of 10 MHz, and a power consumption of about 90 mW, with a supply voltage of 1.8 V, resulting in a figure of merit (FoMBP) as low as about 0.15 pJ/conversion-level.

In this paper we present a 1.6-GHz pipeline A/D converter (ADC) for digital television and digital broadcast satellite. The ADC, designed in a standard 65-nm CMOS technology, achieves in simulation a signal-to-noise and distortion ratio (SNDR) of 54.3 dB (8.73 ENOB), over a signal bandwidth of 615 MHz. The ADC core consumes 430 mW from 1-V and 2.5-V power supplies. In order to achieve the required sampling frequency, the proposed ADC exploits a time-interleaved architecture with four paths. Each path consists of a 10-bit pipeline ADC with four stages (a 3.5-bit stage, a 1.5-bit stage, a 2.5-bit stage and a final 4-bit flash stage). Operational amplifier sharing is adopted in the last two stages for reducing the power consumption. The active area of the chip is 2.7 × 3.2 mm2.

This paper presents an integrated smart label for tracing food information and monitoring its preservation conditions. The system includes humidity, temperature, and light intensity sensors with the respective interface circuits, an A/D converter, and a 13.56-MHz RFID transponder for transmitting and receiving data, as well as for gathering from an external reader the energy for recharging the on-board microbattery and powering the transmitter. The proposed systems, designed in a 0.18-mum CMOS technology, achieves in simulation the required performance, in terms of functionality, accuracy, and power consumption.

This paper presents a complete interface circuit for capacitive MEMS microphones, consisting of the cascade of a preamplifier, a second-order, multi-bit analog SigmaDelta modulator, and a fourth-order, single-bit digital SigmaDelta modulator. The complete interface circuit features a current consumption of 574 muA from a 3.3-V power supply, achieving a signal-to-noise and distortion ratio (SNDR) of 87.5 dB. The feed-forward technique has been used in the analog SigmaDelta modulator, to relax the requirements of the operational amplifiers. The proposed MEMS microphone interface circuit is designed in a 0.35-mum CMOS technology. Post-layout and Montecarlo simulation results of the overall circuit are reported to validate the performance.

In recent years, continuous research efforts have been concentrating in increasing ΣΔ modulators operating frequency, while still reducing their power consumption. Indeed, when the ΣΔ modulator figure of merit (FoM) is less than 1 pJ/conversion, the decimation filter power consumption becomes a critical parameter. This paper presents a low power sin3FIR filter for ΣΔ modulators. The proposed filter implements a decimation by 4, operating at 64 MHz and consumes only 0.1 pJ/sample processed. The circuit has been implemented and simulated in a 0.18-μm CMOS technology, showing an overall power consumption reduction of about 67% with respect to a conventional design. Finally, a silicon area reduction of 17% in the combinatory part of the filter can also be achieved.

In this paper an integrated CMOS front-end circuit for a micro-integrated fluxgate magnetometer is proposed. The system is based on excitation block, that feeds the excitation coil of the sensor and a read-out block that sense the voltage of the pick-up coils. To sense the output signal, the second harmonic detection principle has been chosen to achieve a good compromise between power consumption and noise requirements. An integrated low pass Sallen-Key filter has been used to extract the dc signal after the demodulation. The preliminary measurements, performed with a PCB sensor, show a sensitivity of 920 V/T and a linearity error of 6% full scale. The circuit has been realized in a standard 0.35 mum CMOS process. The power consumption is 8 mW @ 3.3V for the excitation and read-out parts and unit and 42 mW @ 5V for the output power stage

This paper presents a reconfigurable analog baseband channel for multistandard receivers. The circuit, consisting of two variable gain amplifiers and a low-pass filter, fulfills the requirements of GSM, WCDMA (UMTS), WLAN (IEEE 802.11a/b/g), and Bluetooth. The gain, bandwidth and power consumption of the circuit are changed through a digital control word depending on the selected standard. Simulation results, including all of the tests prescribed by the different standards, confirm the validity of the proposed solution. The in-band IIP3 evaluated with maximum gain (68dB/39dB) is 5dBm/1dBm for UMTS/WLAN respectively, while the power consumption is 51.7mW/55mW in the two cases

In this paper an integrated wide-range gas sensor interface based on a resistance-to-number converter is presented. The circuit in transistor level simulations achieves a precision of about 0.5% over a range of 5 decades, i.e. [1kOmega-100MOmega] without requiring any calibration or autoranging, while reconfiguring the circuit and performing a limited calibration, the dynamic range is expected to rise up to 7 decades, e.g. [100Omega-1GOmega]. The presented technique exploits an integrator-based controlled oscillator, whose main time constant is function of the applied resistance value, named Rsens. The state of the art of this measurement method has been improved by separating the oscillator circuit from the sensing device, leading to higher linearity-speed response factor. The maximum conversion time is 5 seconds, when sensing the highest resistance values, i.e. Rsens=100MOmega, while for the lower half-range (Rsensles320kOmega) the conversion time is only 15ms

This paper presents a novel 10-bit pipeline A/D converter for low noise, self-triggered applications. The proposed A/D converter does not require any timing signal (clock) in order to carry out the conversion, assuming that a sampled signal is provided at the input. The circuit basically operates as "combinatorial logic", propagating the partial conversions and the residues through the various stages asynchronously. The presented ADC has been designed in a standard 0.35 mum CMOS technology and the conversion period is lower than 500 ns (i.e. 2 MHz data rate). The power consumption is 39 mW from a 3.3 V power supply. The total chip area without pads is 2.24 mm2

Design automation for analog/mixed-signal (AIMS) circuits and systems is still lagging behind compared to what has been reached in the digital area. As System-on-Chip (SoC) designs include analog components in most cases, these analog parts become even more a bottleneck in the overall design process. The paper is dedicated to latest R&D activities within the MEDEA+ project ANASTASIA+. Main focus will be the development of seamless top-down design methods for integrated analog and mixed-signal systems and to achieve a high level of automation and reuse in the A/MS design process. These efforts are motivated by the urgent need to close the current gap in the industrial design flow between system specification and design on the one hand and block-level circuit design on the other hand. The paper will focus on three subtopics starting with the top-down design flow with applications from circuit sizing, design centering, and automated behavioral modeling. The next part focuses on modeling and simulation of specific functionalities in sigma-delta design while the last section is dedicated to a mixed-signal System-on-Chip design environment.

A digital-to-analog converter system compliant with the requirements of software radio transmission interfaces is presented. The system, through a proper combination of interpolation, digital filtering and data conversion allows us to relax the speed requirements of the analog and the digital section while fully satisfying the specifications. A design example and high level simulation results are presented.

The design of low-power rail-to-rail output buffers for high capacitive loads is critical. In particular, control of the output current, constant input transconductance and output stage driving must be well confined. In this paper we discuss the major design constraints and present a new topology for a CMOS rail-to-rail output buffer. The experimental results show that the proposed architecture is suitable for input-output signals within the full dynamic.

In this paper we propose an A/D converter for smart sensor read-out systems with limited bandwidth. The system can be associated with various sensors in the case where digital output and high resolution are required. The converter is intended to be cointegrated with IC compatible microsensors. An application of the proposed A/D converter is demonstrated in combination with a two dimensional magnetic vector probe for accurate measurement of the angle of a magnetic field parallel to the chip plane. A two dimensional magnetotransistor serves as sensing element. The converter can be configured to achieve the angle calculation with good accuracy. This system is designed to be used in automotive and drive applications. We successfully implemented the proposed A/D converter in a standard 2 /spl mu/m CMOS technology together with a two dimensional magnetic vector probe.

In this paper we present a new modulator architecture for A/D conversion. This modulator allows a great simplification of the analog front end at the expense of a more complex digital signal processing for the bit stream decoding. Moreover, the system can be partitioned into two blocks communicating through noise immune signal lines. These two features, are very advantageous for sensor interfaces in remote locations and where only a minimal amount of circuitry can be co-integrated with the sensor. Extensive computer simulations demonstrate the feasibility of this approach.>

In this paper we propose new approach to operate Suppressed Sidewall Injection dual collector Magnetotransistor (SSIMT), which allows one to reduce the power consumption and to implement directly switched capacitor signal-processing functions. This is obtained using charge instead of current to drive the device. Because of the clocked operation, the static power dissipation is eliminated and a sampled signal is obtained directly from the sensor. The proposed approach has been experimentally verified and the obtained results are presented.>