This demo illustrates the processing capabilities of the Eye-RIS vision systems; specifically using the Eye-RIS v1.2. These systems employ an AnaFocus's a proprietary architecture where processing is realized in two steps. The first stage of the architecture embeds sensors, parallel processing analog and mixed-signal circuitry, control circuitry and memory. This front-stage is implemented through dedicated bio-inspired chips. The second stage of the Eye-RIS vision system architecture is a digital microprocessor. The combination of parallel preprocessing and serial post-processing makes the Eye-RIS systems very efficient particularly the Eye-RIS systems are capable to close the sensor-processing-actuation loop at a high speed. In this demo, the Eye-RIS v1.2 is used to recognize data matrix codes at more than 200 codes/sec rate.

Some features of the biological retina can be modelled by a 2-layer cellular neural network (CNN) composed of locally connected elementary nonlinear processors. In order to explore these complex spatiotemporal dynamics for image processing, a prototype chip has been designed and fabricated in a 0.5 microm CMOS technology. Design challenges, trade-offs, the building blocks and the tests results for this system with 0.5 x 10(6) transistors, most of them operating in analog mode, are presented in this paper.

This paper presents a new generation 128x128 Focal-Plane Analog Programmable Array Processor -FPAPAP, from a system level perspective. It has been manufactured in a 0.35 microm standard digital 1P-5M CMOS technology. It has been designed to achieve the high-speed and moderate-accuracy -8b- requirements of most real time -early-vision applications. External data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. It achieves peak computing values of 0.33TeraOPS while keeping power consumption at reasonable limits -82.5GOPS/W. Preliminary experimental results are also provided in the paper.

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.

A bio-inspired model for an analog parallel array processor (APAP), based on studies on the vertebrate retina, permits the realization of complex spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed in 0.5 /spl mu/m CMOS. Design challenges, trade-offs and the building blocks of such a high-complexity system (0.5/spl times/10/sup 6/ transistors, most of them operating in analog mode) are presented in this paper.

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynam- ics in VLSI. This model mimics the way in which images are pro- cessed in the visual pathway, rendering a feasible alternative for the implementation of early vision applications in standard tech- nologies. A prototype chip has been designed and fabricated in a 0.5(cid:22)m standard CMOS process. Computing power per area and power consumption is amongst the highest reported for a single chip. Design challenges, trade-o(cid:11)s and some experimental results are presented in this paper.

This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new prototype, called CNNUC3, follows the cellular neural network universal machine computing paradigm. Due to its very advanced features and algorithmic capabilities, this chip has been demonstrated to be able to perform not only linear templates executions, but also to be very adequate for the implementation of non-linear templates by using a decomposition method. This paper focus on the application examples of the execution of non-linear templates with the CNNUC3 prototype. A brief description of the theoretical background is also presented in the paper.

Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided medical diagnosis, or telesurgery require an enormous computing power-in the order of trillions of operations per second (TeraOPS). Compared with conventional digital technology, cellular neural/nonlinear network (CNN)-based computing is capable of realizing these TeraOPS-range image processing tasks in a cost-effective implementation. To exploit the computing power of the CNN Universal Machine (CNN-UM), the CNN chipset architecture has been developed-a mixed-signal hardware platform for CNN-based image processing. One of the nonstandard components of the chipset is the cache memory of the analog array processor, the analog random access memory (ARAM). This paper reports on an ARAM chip that has been designed and fabricated in a 0.5-/spl mu/m CMOS technology. This chip consists of a fully addressable array of 32/spl times/256 analog memory registers and has a packing density of 637 analog-memory-cells/mm/sup 2/. Random and nondestructive access of the memory contents is available. Bottom-plate sampling techniques have been employed to eliminate harmonic distortion introduced by signal-dependent feedthrough. Signal coupling and interaction have been minimized by proper layout measures, including the use of protection rings and separate power supplies for the analog and the digital circuitry. This prototype features an equivalent resolution of up to 7 bits-measured by comparing the reconstructed waveform with the original input signal. Measured access times for writing/reading to/from the memory registers are of 200 ns. I/O rates via the l6-line-wide I/O bus exceed 10 Msamples/s. Storage time at room temperature is in the 80 to 100 ms range, without accuracy loss.

This paper describes the design of a programmable Cellular Neural Network (CNN) chip, with additional functionalities similar to those of the CNN Universal Chip. The prototype, which contains 1024 cells, has been designed in a 1.0 /spl mu/m, n-well CMOS technology. A careful selection of the topology and design parameters has resulted in a cell density of 31 cells/mm/sup 2/ and an accuracy in the weight values in the range of 7-8 bits. Adaptive techniques have been employed to ensure accurate external control and system robustness against process-parameter variations.