This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, $2^i$, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.

Controlled random tests, methods of their generation, as well as their application to the testing of both hardware and software systems are discussed. Available evidences suggest that high computational complexity is one of the main drawback of these methods. Therefore we propose a technique to overcome this problem. In the paper, we introduce the concept of multiple controlled random tests ( MCRT) and examine various numerical characteristics in terms of the development of those tests. We prove the effectiveness of the Euclidean distance, as well as we propose an easy computational method of its calculation, in the process of constructing MCRT. The presented approach is evaluated through the experimental study in the context of testing of Random Access Memory (RAM).

Antirandom testing is a variation of pure random testing, which is the process of generating random patterns and applying it to a system under test (both software systems and hardware systems). However, research studies have shown that pure random testing is relatively less effective at fault detection than other testing techniques. Antirandom testing improves the fault-detection capability of random testing by employing the location information of previously executed test cases. In antirandom testing we select test case such that it is as different as possible from all the previous executed test cases. Unfortunately, this method essentially requires enumeration of the input space and computation of each input pattern when used on an arbitrary set of existing test data. This avoids scale-up to large test sets and (or) long input vectors. The objective of this paper is to find a more efficient method of the test generation which does not need any computation. The key idea of proposed approach is an iterative application of the short antirandom tests where the first test vector in each iteration is generated randomly. Moreover, we propose a new metric the Maximal Minimal Hamming Distance (MMHD) which allows us to define an optimal antirandom test with restricted number of patterns. Experimental results are given to evaluate the performance of the new approach.

Antirandom testing has proved useful in a series of empricial evaluations. It improves the fault-detection capability of random testing by employing the location information of previously executed test cases. In antirandom testing we select test pattern (test vector) such that it is as different as possible from all the previous executed test cases. Unfortunately, this method essentially requires enumeration of the input space and computation of each input vector when used on an arbitrary set of existing test data. This avoids scale-up to large test sets and (or) long input vectors. In this paper, we propose a new algorithm for antirandom test generation that is computationally feasible for BIST (Built In Self Test) tests. As the fitness function we use Maximal Minimal Hamming Distance (MMHD) rather than standard Hamming distance as is used in the classical approach. This allows to generate the most efficient test vectors in term of weighted number of generated k-bits tuples. Experimental results are given to evaluate the performance of the new approach.