Demo Data from VLDB 2026 / reviewers in the wild / expert
Raymond P. Voith
dblp:81/5886
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1977
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 91% Integrated circuit design · 9% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
logic synthesis |
0.0 | 3 | 1977 | Minimum Universal Logic Module Sequential Circuits with Decoders · IEEE Trans. Computers 1977 ULM Implicants for Minimization of Universal Logic Module Circuits · IEEE Trans. Computers 1977 B 74-32 Digital Design · IEEE Trans. Computers 1974 |
Electronic design automation › logic synthesis › logic network design
universal logic modules |
0.0 | 2 | 1977 | Minimum Universal Logic Module Sequential Circuits with Decoders · IEEE Trans. Computers 1977 ULM Implicants for Minimization of Universal Logic Module Circuits · IEEE Trans. Computers 1977 |
Electronic design automation › logic synthesis › circuit optimization
circuit minimization |
0.0 | 2 | 1977 | ULM Implicants for Minimization of Universal Logic Module Circuits · IEEE Trans. Computers 1977 Minimum Universal Logic Module Sequential Circuits with Decoders · IEEE Trans. Computers 1977 |
Electronic design automation › logic synthesis
sequential circuit synthesis |
0.0 | 1 | 1977 | Minimum Universal Logic Module Sequential Circuits with Decoders · IEEE Trans. Computers 1977 |
Integrated circuit design
digital system design |
0.0 | 1 | 1974 | B 74-32 Digital Design · IEEE Trans. Computers 1974 |
Methods — techniques the papers use, named apart from their topics
prime implicants · 0.0decoder-based synthesis · 0.0ULM implicants · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1977 | ULM Implicants for Minimization of Universal Logic Module CircuitsabstractIn this paper a method is developed for circuit minimization using the universal logic modules (ULM's) of Yau and Tang. This objective is obtained by using an extension of prime implicants termed ULM implicants. Each ULM implicant implies one possible saving of a module in the tree structure implementing a function. The method is developed for the ULM(l) and an extension to the higher order ULM(p) is discussed. Raymond P. Voith |
IEEE Trans. Computers | 1 |
| 1977 | Minimum Universal Logic Module Sequential Circuits with DecodersabstractUniversal logic modules of n variables (ULM-n) can be used to synthesize sequential machines. It has been shown that any machine can be realized using delayed ULM's and OR gates. Addition of an n -to-2n decoder allows minimization of the number of ULM's necessary. Raymond P. Voith |
IEEE Trans. Computers | 1 |
| 1974 | B 74-32 Digital DesignabstractThis book is very practically oriented. Implementations and methods for a wide range of digital design problems are presented. Simplifying assumptions of theoretic approaches are discussed, although the classical theoretical approaches are not always developed. If a reader comes to this book with some appreciation of the theoretic approaches, it may provide much insight into the practical problems of design, as well as provide a reference for many alternative approaches to digital design problems. Raymond P. Voith |
IEEE Trans. Computers | 1 |