Demo Data from VLDB 2026 / reviewers in the wild / expert
Adrian Colbrook
dblp:81/5964
· DBLP profile ↗
6ranked-venue papers
4as first author
0since 2021 · last 1999
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-authorSoftware engineering, systems software and programming languages · 3 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Parallel and multicore computing · 78% Performance modeling and evaluation · 22% | |
| Theoretical computer science
1 paper |
Algorithms and data structures · 100% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing
concurrent data structures |
0.0 | 1 | 1996 | Algorithms for Search Trees on Message-Passing Architectures · IEEE Trans. Parallel Distributed Syst. 1996 |
Parallel and multicore computing › concurrent data structures
concurrent search trees |
0.0 | 1 | 1996 | Algorithms for Search Trees on Message-Passing Architectures · IEEE Trans. Parallel Distributed Syst. 1996 |
Parallel and multicore computing › parallel architecture
message-passing architecture |
0.0 | 1 | 1996 | Algorithms for Search Trees on Message-Passing Architectures · IEEE Trans. Parallel Distributed Syst. 1996 |
Parallel and multicore computing › parallel algorithms › parallel algorithm design
MIMD algorithms |
0.0 | 1 | 1996 | Algorithms for Search Trees on Message-Passing Architectures · IEEE Trans. Parallel Distributed Syst. 1996 |
Performance modeling and evaluation › simulation
parallel architecture simulation |
0.0 | 1 | 1992 | PROTEUS: A High-Performance Parallel-Architecture Simulator · SIGMETRICS 1992 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1992 | PROTEUS: A High-Performance Parallel-Architecture Simulator · SIGMETRICS 1992 |
Algorithms and data structures › data structure design › search structures › search trees
balanced search trees |
0.0 | 1 | 1996 | Algorithms for Search Trees on Message-Passing Architectures · IEEE Trans. Parallel Distributed Syst. 1996 |
Parallel and multicore computing › multiprocessor system
MIMD multiprocessor |
0.0 | 1 | 1992 | PROTEUS: A High-Performance Parallel-Architecture Simulator · SIGMETRICS 1992 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1999 | The European Porting Project - demonstrating industrial relevance of parallel HPCabstractThe European Porting Project was a European Commission ESPRIT project aimed at increasing awareness and confidence in parallel high-performance computing and networking technology in European industry. This was achieved by porting 38 large serial commercial and industrial codes to parallel message-passing architectures, resulting in significant industrial and commercial impact within a 2-year timeframe. We present brief descriptions and performance results for three of these codes, applications in the fields of pharmaceutics, electromagnetics and cartoon animation, and describe the business benefits that have been derived from the development of these codes. Copyright © 1999 John Wiley & Sons, Ltd. Stephen H. Brindle, Adrian Colbrook, John A. Elliott, Daron Green, Francis Wray |
Concurr. Pract. Exp. | 2 |
| 1996 | Algorithms for Search Trees on Message-Passing ArchitecturesabstractIn this paper we describe a new algorithm for maintaining a balanced search tree on a message-passing MIMD architecture; the algorithm is particularly well suited for implementation on a small number of processors. We introduce a (2/sup B-2/, 2/sup B/) search tree that uses a bidirectional ring of O(log n) processors to store n entries. Update operations use a bottom-up node-splitting scheme, which performs significantly better than top-down search tree algorithms. The bottom-up algorithm requires many fewer messages and results in less blocking due to synchronization than top-down algorithms. Additionally, for a given cost ratio of computation to communication the value of B may be varied to maximize performance. Implementations on a parallel-architecture simulator are described. Adrian Colbrook, Eric A. Brewer, Chrysanthos Dellarocas, William E. Weihl |
IEEE Trans. Parallel Distributed Syst. | 1 |
| 1992 | PROTEUS: A High-Performance Parallel-Architecture SimulatorabstractPROTEUS is a high-performance simulator for MIMD multiprocessors. It is fast, accurate, and flexible: it is one to two orders of magnitude faster than comparable simulators, it can reproduce results from real multiprocessors, and it is easily configured to simulate a wide range of architectures. PROTEUS provides a modular structure that simplifies customization and independent replacement of parts of architecture. There are typically multiple implementations of each module that provide different combinations of accuracy and performance; users pay for accuracy only when and where they need it. Finally, PROTEUS provides repeatability, nonintrusive monitoring and debugging, and integrated graphical output, which result in a development environment superior to those available on real multiprocessors. Eric A. Brewer, Chrysanthos Dellarocas, Adrian Colbrook, William E. Weihl |
SIGMETRICS | 3 |
| 1991 | An Algorithm for Concurrent Search Trees
Adrian Colbrook, Eric A. Brewer, Chrysanthos Dellarocas, William E. Weihl |
ICPP (3) | 1 |
| 1990 | Data abstraction in a software re-engineering reference modelabstractThe process of software reengineering must incorporate techniques for manipulating software which is imperative, declarative, or functional in nature. This generality needs a mechanism for deriving the original requirements of the underlying data structures contained within the source code itself. A reference model is proposed from which it is possible to derive the necessary techniques required to implement such a mechanism. The proposed model, the source code reengineering reference model (SCORE/RM), consists of eight layers (encapsulation, transformation, normalization, interpretation, abstraction, causation, regeneration, and certification) which provide a step-by-step approach to rationalizing the software, comprehending its functions and requirements, and rebuilding it according to well-established practices of software engineering. Such a framework can then be used to provide improved maintenance capability, language translation, retrospective standardization of the code and documentation, code migration onto parallel architectures, and formal specification.> Adrian Colbrook, Colin Smythe, A. Darlison |
ICSM | 1 |
| 1989 | The retrospective introduction of abstraction into softwareabstractThe reengineering of program control flow schemas is described, although a widely advocated preventive maintenance technique, fails to address the underlying problems of software which contains poorly structured data. A technique that facilitates the retrospective introduction of abstract data types into existing systems is proposed, and the corresponding software tool to aid this process is presented. The resulting source code is structured in terms of both data and control flow, thereby significantly promoting the ease of maintenance.> Adrian Colbrook, Colin Smythe |
ICSM | 1 |