This manuscript details the design and analysis of a CMOS rectifier in TSMC 65 nm for the 5G NR2 band and aims to overcome the challenge of achieving high rectified voltage while optimizing for PCE (power conversion efficiency). Using a frequency-scaled testbench, the transistor currents are investigated, providing key insights on the rectification mechanism that guide the design. The testbench is then used to determine the optimal number,$N$, of summing rectifiers to be used in a power splitting and voltage summing strategy that maximizes PCE for high target output voltage. In addition, a unit-cell rectifier design highlights how to target a specific output voltage while maintaining dc power matching for optimal PCE. Two rectifiers are presented: a unit-cell rectifier targeting -13 dBm and an$N$-scaled rectifier targeting$-$10 dBm. Both designs achieve a PCE of 15% at 27.5 GHz, while the former achieves 200 mV and the latter achieves 400 mV output voltage, for their respective target input powers. Finally, a survey of rectifiers operating around 30 GHz is presented where a x2 improvement over the current state-of-the-art is ascertained.

In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400mm2die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

In this paper, we propose a new way of implementing on-chip global interconnect that would meet stringent challenges of core-to-core communications in latency, data rate, and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitation of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I) through on-chip differential transmission lines. The physical implementation of RF-I and its projected performance versus overhead as the function of CMOS technology scaling are discussed as well

As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of radio frequency interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has considered the latency advantage of RF-I, we demonstrate three further advantages of RF-I: (1) RF-I bandwidth can be flexibly allocated to provide an adaptive NoC, (2) RF-I can enable a dramatic power and area reduction by simplification of NoC topology, and (3) RF-I provides natural and efficient support for multicast. In this paper, we propose a novel interconnect design, exploiting dynamic RF-I bandwidth allocation to realize a reconfigurable network-on-chip architecture. We find that our adaptive RF-I architecture on top of a mesh with 4B links can even outperform the baseline with 16B mesh links by about 1%, and reduces NoC power by approximately 65% including the overhead incurred for supporting RF-I.