Researchers have explored different ways to improve large language models (LLMs)' capabilities via dummy token insertion in contexts.However, existing works focus solely on the dummy tokens themselves, but fail to leverage the inherent sentence-level structure of natural language.This is a critical oversight, as LLMs acquire linguistic capabilities through exposure to human-generated texts, which are inherently structured at the sentence level.Motivated by this gap, we propose an approach that inserts delimiters at sentence boundaries in LLM inputs, which not only integrates dummy tokens into the context, but also facilitates LLMs with sentence-by-sentence processing behavior during reasoning.Two concrete methods: (1).In-context learning and (2).Supervised finetuning are experimented using 7B models to 600B Deepseek-V3.Our results demonstrate consistent improvements across various tasks, with notable gains of up to 7.7% on GSM8k and 12.5% on DROP.Furthermore, the fine-tuned LLMs can incorporate sentence awareness evidenced by their internal representations.Our work establishes a simple yet effective technique 1 for enhancing LLM's capabilities, offering promising directions for cognitive-inspired LLM enhancement paradigm.

Existing for audio- and pose-driven human animation methods often struggle with stiff head movements and blurry hands, primarily due to the weak correlation between audio and head movements and the structural complexity of hands. To address these issues, we propose VividAnimator, an end-to-end framework for generating high-quality, half-body human animations driven by audio and sparse hand pose conditions. Our framework introduces three key innovations. First, to overcome the instability and high cost of online codebook training, we pre-train a Hand Clarity Codebook (HCC) that encodes rich, high-fidelity hand texture priors, significantly mitigating hand degradation. Second, we design a Dual-Stream Audio-Aware Module (DSAA) to model lip synchronization and natural head pose dynamics separately while enabling interaction. Third, we introduce a Pose Calibration Trick (PCT) that refines and aligns pose conditions by relaxing rigid constraints, ensuring smooth and natural gesture transitions. Extensive experiments demonstrate that Vivid Animator achieves state-of-the-art performance, producing videos with superior hand detail, gesture realism, and identity consistency, validated by both quantitative metrics and qualitative evaluations.

Conventional duty-cycle-based (DCB) maximum power point tracking (MPPT) schemes generally assume a 50% duty cycle for operation at the maximum power point (MPP). However, due to nonideal losses in the piezoelectric transducer (PZT), such as dielectric loss, mechanical damping, and rectifieroff-state leakage, the actual optimal duty cycle deviates from this nominal value. This brief develops a theoretical model that incorporates these losses, which is derived, analyzed, and experimentally validated using a piezoelectric energy harvester (PEH) integrated with a bias-flip MPPT regulating rectifier (BMRR). Measurement results show that the optimal duty cycle ranges from 42.3% to 42.8%, under which the rectifier delivers 1.1 times the output power compared to operation at a fixed 50% duty cycle. Furthermore, the proposed rectifier achieves a peak power conversion efficiency (PCE) of 89.6% and demonstrates a 7.4-fold improvement in energy extraction compared to a full-bridge rectifier (FBR).

Electromagnetic interference (EMI) is an inevitable issue in power electronics applications. Although many kinds of solutions have been presented to attenuate EMI noise, there is still little research about the EMI suppression scheme utilized in multimode primary-side regulation (PSR) flyback converters. Targeting EMI regulation in multimode PSR flyback converter, a combo EMI suppression scheme comprised of frequency modulation and dual-slope gate driver is adopted to meet stringent EMI requirements, simplifying peripheral components and design of EMI filter. The proposed scheme is implemented in$0.18~\mu $m 5/40 V BCD process and occupies a die size (with pads) of$1.05\times 0.8$mm2. The experimental results show that the conducted EMI waveforms with line/neutral polarity can easily comply with regulations. The deviations of the output voltage are within ±1.3% under different inputs and loads while the peak effciency of 90% is achieved.

The power over Ethernet (PoE) technology has gained intensive attention in networking market owing to the advantages of compactness, flexibility, and cost in application. The automatic maintain power signature (MPS) function specified by IEEE standard extracts the periodic pulsed current to enable applications requiring low power modes. However, a large driving capacity is required due to a large MPS current above 10 mA, sacrificing a certain area. This brief proposes an adaptive MPS scheme, which reuses existing class regulator and delay timer to source a pulsed MPS current to meet the MPS requirements, saving an area of 0.0104 mm2. The proposed MPS scheme has been fabricated in 0.18-$\mu $m 120-V BCD process and the area is$1.37\times 1.00$mm2. The experimental results show that the proposed PoE interface draws a pulsed current with a period of 312 ms and 25.6% duty cycle to address the issue of MPS absence in very low-power standby modes.

Human and model-generated texts can be distinguished by examining the magnitude of likelihood in language.However, it is becoming increasingly difficult as language model's capabilities of generating human-like texts keep evolving.This study provides a new perspective by using the relative likelihood values instead of absolute ones, and extracting useful features from the spectrum-view of likelihood for the human-model text detection task.We propose a detection procedure with two classification methods, supervised and heuristic-based, respectively, which results in competitive performances with previous zero-shot detection methods and a new state-of-the-art on short-text detection.Our method can also reveal subtle differences between human and model languages, which find theoretical roots in psycholinguistics studies.

In order to improve the efficiency over a wide load range, a power converter of the Internet of Things (IoT) usually works in dual modes, which are pulsewidth modulation (PWM) and pulse frequency modulation (PFM). A mixed load detection scheme is adopted to enable the appropriate modes under different loads, whose analog detector has an accurate detection in the heavy load, and the digital load detection improves the light-load efficiency. When the power converter operates in different modes, the control loops are different. Meanwhile, a seamless mode transition technique (SMTT) is presented in this article to improve the transient response during mode change between PWM and PFM. A test chip was fabricated in a 0.18-$\mu $m standard CMOS process, and the chip area is$1.59\times 1.37$mm2. The experimental results show that the efficiency is above 85.3% under$V_{\text {IN}}=3.3$V,$V_{\text {OUT}}=1.8$V, and in the load range from 1 to 300 mA, while peak efficiency can reach 96.1% at 100-mA load. Compared to the case without the proposed technique, the under/overshoot voltage can be reduced by above 55% during the mode transition.

This article presents a constant voltage control scheme to improve the transfer efficiency and output voltage accuracy for single-stage AC-DC converters. The proposed scheme also has the advantage of low cost because of the simple application and few peripheral devices. To realize above features, the peak current and frequency curves with high efficiency are selected by analyzing the power losses of the applied topology. A voltage self-compensation circuit is designed to improve the output accuracy, especially the output voltage below 5V. Furthermore, a multi-stage startup circuit is also proposed to reduce the output voltage overshoot. To verify the feasibility of the proposed constant voltage control scheme, a BUCK controller adopting the proposed control scheme has been designed and fabricated with$0.18~\mu \text{m}$BCD process. Using the proposed controller, the peak efficiency of the prototype can reach as high as 66.9%, 78.9% and 82.8% under 115Vac input and 3.3V@300mA, 5V@300mA and 12V@300mA respectively. The load regulation is counted to be within ±1%.

This paper presents a multi-mode boost converter to achieve the high efficiency over a wide input voltage range for thermoelectric energy harvesting (TEH) applications. Under high, medium, and low input voltages, continuous conduction mode (CCM), critical conduction mode (CRM), and discontinuous conduction mode (DCM) are adopted to improve the conversion efficiency, respectively. Moreover, a constant peak current (CPC) control scheme is proposed to realize high efficiency under ultra-low input voltage. The proposed converter is implemented in a$0.18 \mu \text{m}$standard CMOS process, which occupies a chip core area of about 1.0 mm$\times0.9$mm. It achieves >60% efficiency in the range of TEG open-circuit voltage$V_{S}$from 20 mV to 500 mV, and a peak efficiency of 91.4%. Moreover, after the startup is completed, an efficiency of 37.1% under the$V_{S}$as low as 10 mV can be achieved.

A dual-mode controlled dc-dc controller with power over Ethernet (PoE) interface for power device (PD) is presented that is designed to support drawing power either from an Ethernet cable or from an external auxiliary supply support (ASS). PoE interface supports all the functions that comply with the IEEE802.3af/at standard. Based on bandgap reference structure, a detection comparator is provided to detect input voltage without extra voltage reference. Using a low offset voltage amplifier, a lowloss current-limiting technique is proposed to achieve a high-precision current-limit point. Based on a high-speed comparator and two timing capacitors, an oscillator (OSC) is implemented for better accuracy, and provides the maximum duty cycle (Dmax) and external frequency synchronization. The chip is fabricated in a 0.5-μm 65 V BCD process and occupies a die size (with pads) of 1.79 × 2.76 mm2. The experimental results are measured for an active clamp forward converter with a wide range of dc input voltages from 33 to 57 V, an output voltage of 12 V, and an output power of 30 W. The chip achieves peak power efficiency of 90% and 90.63% on DC and ASS, respectively. The load regulation at different input voltages can be measured to be within ±0.11%. Measurements further show that the peak-to-peak ripple voltage of the chip is 161 mV and the recovery time is less than 1.2 ms for the 2-A load step.