Demo Data from VLDB 2026 / reviewers in the wild / expert
Da Yan 0002
dblp:81/9436-2
· DBLP profile ↗
4ranked-venue papers
4as first author
2since 2021 · last 2022
0000-0001-7741-4576ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-author · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware accelerators and domain-specific architectures · 44% GPUs and heterogeneous computing · 34% High-performance computing · 22% | |
| Software engineering, system software, and programming languages
2 papers |
Compilers and program optimization · 100% |
Topics — the 7 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
GPUs and heterogeneous computing
GPU programming |
0.7 | 2 | 2022 | Simplifying low-level GPU programming with GAS · PPoPP 2021 An LLVM-based open-source compiler for NVIDIA GPUs · PPoPP 2022 |
Compilers and program optimization › code generation
assembly code generation |
0.6 | 1 | 2022 | An LLVM-based open-source compiler for NVIDIA GPUs · PPoPP 2022 |
Compilers and program optimization › accelerator compilation
GPU compiler |
0.6 | 1 | 2022 | An LLVM-based open-source compiler for NVIDIA GPUs · PPoPP 2022 |
Compilers and program optimization
code generation |
0.5 | 1 | 2021 | Simplifying low-level GPU programming with GAS · PPoPP 2021 |
High-performance computing › tensor computation
convolution |
0.4 | 1 | 2020 | Optimizing batched Winograd convolution on GPUs · PPoPP 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator
DNN accelerator |
0.4 | 1 | 2020 | Optimizing batched Winograd convolution on GPUs · PPoPP 2020 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › convolution optimization
winograd convolution |
0.4 | 1 | 2020 | Optimizing batched Winograd convolution on GPUs · PPoPP 2020 |
Methods — techniques the papers use, named apart from their topics
LLVM · 1.1assembly language · 1.0winograd algorithm · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | An LLVM-based open-source compiler for NVIDIA GPUsabstractWe present GASS, an LLVM-based open-source compiler for NVIDIA GPU's SASS machine assembly. GASS is the first open-source compiler targeting SASS, and it provides a unified toolchain for currently fragmented low-level performance research on NVIDIA GPUs. GASS supports all recent architectures, including Volta, Turing, and Ampere. Da Yan 0002, Wei Wang 0030, Xiaowen Chu 0001 |
PPoPP | 1 |
| 2021 | Simplifying low-level GPU programming with GASabstractMany low-level optimizations for NVIDIA GPU can only be implemented in native hardware assembly (SASS). However, programming in SASS is unproductive and not portable. Da Yan 0002, Wei Wang 0030, Xiaowen Chu 0001 |
PPoPP | 1 |
| 2020 | Demystifying Tensor Cores to Optimize Half-Precision Matrix MultiplyabstractHalf-precision matrix multiply has played a key role in the training of deep learning models. The newly designed Nvidia Tensor Cores offer the native instructions for half-precision small matrix multiply, based on which Half-precision General Matrix Multiply (HGEMM) routines are developed and can be accessed through high-level APIs. In this paper, we, for the first time, demystify how Tensor Cores on NVIDIA Turing architecture work in great details, including the instructions used, the registers and data layout required, as well as the throughput and latency of Tensor Core operations. We further benchmark the memory system of Turing GPUs and conduct quantitative analysis of the performance. Our analysis shows that the bandwidth of DRAM, L2 cache and shared memory is the new bottleneck for HGEMM, whose performance is previously believed to be bound by computation. Based on our newly discovered features of Tensor Cores, we apply a series of optimization techniques on the Tensor Core-based HGEMM, including blocking size optimization, data layout redesign, data prefetching, and instruction scheduling. Extensive evaluation results show that our optimized HGEMM routine achieves an average of 1.73× and 1.46× speedup over the native implementation of cuBLAS 10.1 on NVIDIA Turing RTX2070 and T4 GPUs, respectively. The code of our implementation is written in native hardware assembly (SASS). Da Yan 0002, Wei Wang 0030, Xiaowen Chu 0001 |
IPDPS | 1 |
| 2020 | Optimizing batched Winograd convolution on GPUsabstractIn this paper, we present an optimized implementation for single-precision Winograd convolution on NVIDIA Volta and Turing GPUs. Compared with the state-of-the-art Winograd convolution in cuDNN 7.6.1, our implementation achieves up to 2.13X speedup on Volta V100 and up to 2.65X speedup on Turing RTX2070. On both Volta and Turing GPUs, our implementation achieves up to 93% of device peak. Da Yan 0002, Wei Wang 0030, Xiaowen Chu 0001 |
PPoPP | 1 |