VLDB 2026 Research / reviewers in the wild / expert
Taewon Park
dblp:82/10595
· DBLP profile ↗
5ranked-venue papers
4as first author
5since 2021 · last 2025
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 4 · 3 first-author · 4 since 2021Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
2 papers |
Representation and self-supervised learning · 82% Knowledge representation and reasoning · 18% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware reliability and fault tolerance · 75% Hardware accelerators and domain-specific architectures · 25% |
Topics — the 9 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Machine learning › Representation and self-supervised learning › tensor representation
tensor product representation |
1.5 | 2 | 2024 | Discrete Dictionary-based Decomposition Layer for Structured Representation Learning · NeurIPS 2024 Attention-based Iterative Decomposition for Tensor Product Representation · ICLR 2024 |
Hardware accelerators and domain-specific architectures › machine learning accelerator › trustworthy machine learning accelerator
DNN accelerator reliability |
0.9 | 1 | 2025 | PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators · DAC 2025 |
Hardware reliability and fault tolerance › error correction
error-correcting codes |
0.9 | 1 | 2025 | PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators · DAC 2025 |
Hardware reliability and fault tolerance › soft errors
multiple bit upsets |
0.9 | 1 | 2025 | PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators · DAC 2025 |
Hardware reliability and fault tolerance
soft errors |
0.9 | 1 | 2025 | PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN Accelerators · DAC 2025 |
Machine learning › Representation and self-supervised learning › representation learning › compositional representation
compositional representation learning |
0.8 | 1 | 2024 | Attention-based Iterative Decomposition for Tensor Product Representation · ICLR 2024 |
Knowledge, reasoning and agents › Knowledge representation and reasoning
neuro-symbolic reasoning |
0.8 | 1 | 2024 | Discrete Dictionary-based Decomposition Layer for Structured Representation Learning · NeurIPS 2024 |
Machine learning › Representation and self-supervised learning › representation learning
structured representation learning |
0.8 | 1 | 2024 | Discrete Dictionary-based Decomposition Layer for Structured Representation Learning · NeurIPS 2024 |
Machine learning › Representation and self-supervised learning
systematic generalization |
0.5 | 2 | 2024 | Discrete Dictionary-based Decomposition Layer for Structured Representation Learning · NeurIPS 2024 Attention-based Iterative Decomposition for Tensor Product Representation · ICLR 2024 |
Methods — techniques the papers use, named apart from their topics
error correction codes · 0.9key-value dictionary · 0.8iterative decomposition · 0.8discrete dictionary learning · 0.8attention mechanism · 0.8
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN AcceleratorsabstractDeep Neural Networks (DNNs) in safety-critical systems require high reliability. Many systems deploy Error Correction Codes (ECCs) to protect DNNs from memory errors. However, continuous process scaling increases memory errors in severity and frequency, necessitating strong protection against Multi-Bit Upsets (MBUs). This paper proposes Parities of Parities ECC (PoP-ECC), a novel two-tier memory protection scheme designed to provide robust, efficient, and flexible protection against MBUs. PoP-ECC generates Virtual Parities (VPs), which are used to compute secondlevel parities called Parities of Parities (PPs). This two-level ECC structure allows for dynamic error correction tailored to varying error patterns, ensuring system reliability with minimal memory overhead. Our evaluation demonstrates that PoP-ECC can tolerate significantly higher MBU ratios compared to state-of-the-art solutions, with negligible delay, area, and power overhead. Taewon Park, Saeid Gorgin 0001, Dongwhee Kim, Michael B. Sullivan 0001, Jungrae Kim |
DAC | 1 |
| 2024 | Attention-based Iterative Decomposition for Tensor Product RepresentationabstractIn recent research, Tensor Product Representation (TPR) is applied for the systematic generalization task of deep neural networks by learning the compositional structure of data. However, such prior works show limited performance in discovering and representing the symbolic structure from unseen test data because their decomposition to the structural representations was incomplete. In this work, we propose an Attention-based Iterative Decomposition (AID) module designed to enhance the decomposition operations for the structured representations encoded from the sequential input data with TPR. Our AID can be easily adapted to any TPR-based model and provides enhanced systematic decomposition through a competitive attention mechanism between input features and structured representations. In our experiments, AID shows effectiveness by significantly improving the performance of TPR-based prior works on the series of systematic generalization tasks. Moreover, in the quantitative and qualitative evaluations, AID produces more compositional and well-bound structural representations than other works. Taewon Park, Inchul Choi, Minho Lee 0001 |
ICLR | 1 |
| 2024 | Discrete Dictionary-based Decomposition Layer for Structured Representation LearningabstractNeuro-symbolic neural networks have been extensively studied to integrate symbolic operations with neural networks, thereby improving systematic generalization. Specifically, Tensor Product Representation (TPR) framework enables neural networks to perform differentiable symbolic operations by encoding the symbolic structure of data within vector spaces. However, TPR-based neural networks often struggle to decompose unseen data into structured TPR representations, undermining their symbolic operations. To address this decomposition problem, we propose a Discrete Dictionary-based Decomposition (D3) layer designed to enhance the decomposition capabilities of TPR-based models. D3 employs discrete, learnable key-value dictionaries trained to capture symbolic features essential for decomposition operations. It leverages the prior knowledge acquired during training to generate structured TPR representations by mapping input data to pre-learned symbolic features within these dictionaries. D3 is a straightforward drop-in layer that can be seamlessly integrated into any TPR-based model without modifications. Our experimental results demonstrate that D3 significantly improves the systematic generalization of various TPR-based models while requiring fewer additional parameters. Notably, D3 outperforms baseline models on the synthetic task that demands the systematic decomposition of unseen combinatorial data. Taewon Park, Minho Lee 0001 |
NeurIPS | 1 |
| 2022 | Learning Associative Reasoning Towards Systematicity Using Modular Networks
Jun-Hyun Bae, Taewon Park, Minho Lee 0001 |
ICONIP (2) | 2 |
| 2021 | Distributed associative memory network with memory refreshing loss
Taewon Park, Inchul Choi, Minho Lee 0001 |
Neural Networks | 1 |