John P. Gray

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3ranked-venue papers

3as first author

0since 2021 · last 1985

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

3 papers

Electronic design automation · 96% Performance modeling and evaluation · 4%

Topics — the 6 heaviest of 7, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
Electronic design automation high-level synthesis	3	1985	Portability in silicon CAE · DAC 1985 Designing gate arrays using a silicon compiler · DAC 1982 Introduction to silicon compilation · DAC 1979
Electronic design automation › high-level synthesis › hardware compilation silicon compilation	3	1985	Portability in silicon CAE · DAC 1985 Designing gate arrays using a silicon compiler · DAC 1982 Introduction to silicon compilation · DAC 1979
Electronic design automation hardware verification and test	1	1982	Designing gate arrays using a silicon compiler · DAC 1982
Electronic design automation › physical design layout automation	1	1982	Designing gate arrays using a silicon compiler · DAC 1982
Electronic design automation physical design	1	1982	Designing gate arrays using a silicon compiler · DAC 1982
Performance modeling and evaluation simulation	1	1982	Designing gate arrays using a silicon compiler · DAC 1982

Year	Publication	Venue	Position
1985	Portability in silicon CAE abstract The proliferation of engineering workstations and silicon foundries has made portability a critical issue for today's integrated circuit engineer. The two forms of such portability must be clearly distinguished and addressed separately. This paper describes a way of protecting investment in designs and design tools by using (i) portable compiler technology and (ii) silicon compilation techniques, to give the engineer the options of machine and process portability. John P. Gray, John Hunter	DAC	1
1982	Designing gate arrays using a silicon compiler abstract This paper describes a programming environment in which gate array designs can be developed. It allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. The principle features of this are a high-level language for design description, completely automatic layout, and an integrated simulator. The total package can be referred to as a silicon compiler in the gate array design style. John P. Gray, Irene Buchanan, Peter Salkeld Robertson	DAC	1
1979	Introduction to silicon compilation John P. Gray	DAC	1