Peak to average power (PAPR) reduction of OFDM signals is critical in order to improve power amplifier (PA) efficiency in base stations. For massive MIMO, the complexity of these methods can become a real bottleneck in implementing low power digital signal processing chains. In this work, we consider an antenna reservation technique, which uses a low complexity clipping method to reduce signal peaks and leverages the benefit of massive antennas, by reserving a subset of antennas in order to compensate for the clipping distortion. Reserving antennas on the other hand reduces the potential array gain in the massive MIMO system, complicating the application of antenna reservation. This work explores various design space parameters in antenna reservation such as number of reserved antennas, amount of peak reduction and clipping methods. We investigate the impact of these parameters on the error vector magnitude at the user and on the adjacent channel power ratio at both transmitter and user positions. Our results enable a deeper understanding of antenna reservation as a low complexity PAPR reduction method in massive MIMO systems.

This work analyzes the nonlinear effects in the track and hold circuit applied in high-speed ADCs or RF sampling receiver (RX) front-ends. Non-ideal effects inside the main sampling NMOS switch are studied. Parasitic varactor and sampling on-resistance modulation effects are analyzed through frequency domain Volterra series and the EKV MOS transistor model. Polynomial curve fitting is applied showing that the on-resistance modulation dominates. Finally, a novel bootstrap circuit is proposed with a fast settling time and high bootstrap voltage in a 22 nm FD-SOI CMOS technology, with its settling time analyzed using the Elmore delay model.

Mobile communications have been undergoing a generational change every ten years or so. However, the time difference between the so-called “G's” is also decreasing. While fifth-generation (5G) systems are becoming a commercial reality, there is already significant interest in systems beyond 5G, which we refer to as the sixth generation (6G) of wireless systems. In contrast to the already published papers on the topic, we take a top-down approach to 6G. More precisely, we present a holistic discussion of 6G systems beginning with lifestyle and societal changes driving the need for next-generation networks. This is followed by a discussion into the technical requirements needed to enable 6G applications, based on which we dissect key challenges and possibilities for practically realizable system solutions across all layers of the Open Systems Interconnection stack (i.e., from applications to the physical layer). Since many of the 6G applications will need access to an order-of-magnitude more spectrum, utilization of frequencies between 100 GHz and 1 THz becomes of paramount importance. As such, the 6G ecosystem will feature a diverse range of frequency bands, ranging from below 6 GHz up to 1 THz. We comprehensively characterize the limitations that must be overcome to realize working systems in these bands and provide a unique perspective on the physical and higher layer challenges relating to the design of next-generation core networks, new modulation and coding methods, novel multiple-access techniques, antenna arrays, wave propagation, radio frequency transceiver design, and real-time signal processing. We rigorously discuss the fundamental changes required in the core networks of the future, such as the redesign or significant reduction of the transport architecture that serves as a major source of latency for time-sensitive applications. This is in sharp contrast to the present hierarchical network architectures that are not suitable to realize many of the anticipated 6G services. While evaluating the strengths and weaknesses of key candidate 6G technologies, we differentiate what may be practically achievable over the next decade, relative to what is possible in theory. Keeping this in mind, we present concrete research challenges for each of the discussed system aspects, providing inspiration for what follows.

In this paper, we combine practically verified results from circuit theory with communication-theoretic laws. As a result, we obtain closed-form theoretical expressions linking fundamental system design and environment parameters with the power consumption of analog front ends (AFEs) for communication receivers. This collection of scaling laws and bounds is meant to serve as a theoretical reference for practical low power AFE design. We show how AFE power consumption scales with bandwidth,SNDR, andSIR. We build our analysis based on two well established power consumption studies and show that although they have different design approaches, they lead to the same scaling laws. The obtained scaling laws are subsequently used to derive relations between AFE power consumption and several other important communication system parameters, namely, digital modulation constellation size, symbol error probability, error control coding gain, and coding rate. Such relations, in turn, can be used when deciding which system design strategies to adopt for low-power applications. For instance, we show how AFE power scales with environment parameters if the performance is kept constant and we use these results to illustrate that adapting to fading fluctuations can theoretically reduce AFE power consumption by at least 20x.

A variable gain transimpedance amplifier (TIA) is presented featuring single-ended to differential conversion by means of negative feedback. The proposed topology also ensures stability when amplifier gain is varied. Furthermore, effective input capacitance of the TIA is reduced by using a positive capacitive feedback. The circuit is intended for intermediate frequency (IF) over fiber systems, but can be readily adapted for other applications. When simulated with a photodiode capacitance of 1.4 pF, the TIA exhibits a tunable gain range of 51 to 73dBΩ with a bandwidth of 550 MHz. The circuit designed in a standard 65nm CMOS process consuming 4mA from a 1.2V supply, achieves a spurious free dynamic range (SFDR) of 109dB·Hz2/3at 100 MHz.

In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm2of chip area.

In this paper, we present a new topology to implement a passive 180° phase shifter using on-chip auto-transformer in an SOS process. The measured results indicate a phase variation of less than 2° over the frequency range of 1.8-2.4GHz. An insertion loss of 2.3dB was measured at 2.1GHz. The phase shifter has a small footprint of 0.3 × 0.7mm2, which is almost three times less than a traditional high-pass/low-pass design. Post-layout simulations indicate similar performance in terms of bandwidth, phase accuracy and insertion loss for both circuits. Stacked switches are used to increase the power handling to +20dBm.

This paper presents a robust and low-complexity non-linearity suppression scheme for radio frequency (RF) transceiver building blocks to efficiently mitigate intermodulation distortion. The scheme consists of tunable RF components assisted by an auxiliary path equipped with an adaptive digital signal processing algorithm to provide the tuning control. This proposed concept of digitally-assisted tuning is capable of handling a large range of non-linear behaviours without any complexity increase in the expensive RF circuitry and is robust to process, voltage and temperature variations. A case study on the third order intermodulation of the channel select filter for a full 10MHz Long Term Evolution (LTE) reception bandwidth is used to demonstrate the feasibility and effectiveness of the technique.

This paper presents a study of analog and digital versions of a low complexity channel decoder to investigate the overall performance of both circuits in 65nm CMOS for moderate bit rate applications. Both decoding circuits realize the corresponding decoding algorithm for the convolutional codes generated by the well known 4-state (7,5)8encoder. The two digital and analog implementations are then analyzed for power consumption, offered coding gain, required silicon area and energy efficiency. The simulations show that the analog circuit outperforms its digital version by a factor of 10X at nominal supply voltage for the same throughputs. Furthermore, the analog implementation is 4.6 times smaller in area than its counterpart.

A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-Vτ) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 μW. For low rate applications the decoder consumes only 47 μW at a throughput of 250 kb/s.

This paper presents an analysis on energy dissipation of digital half-band filters operating in the sub-threshold (sub-VT) region with throughput and supply voltage constraints. A 12-bit filter is implemented along with various unfolded structures, used to form a decimation filter chain. The designs are synthesized in a 65 nm low-leakage CMOS technology with various threshold voltages. A sub-VTenergy model is applied to characterize the designs in the sub-VTdomain. The results show that the low-leakage standard-threshold technology is suitable for the required throughput range between 250 Ksamples/s and 2 Msamples/s, at a supply voltage of 260 mV. The total energy dissipation of the filter is 205 fJ per sample.

In this paper, we propose all-digital frequency synthesizer architecture, based on an all-digital SigmaDelta-frequency discriminator. The new all-digital synthesizer is compared to previously published work. The architecture of the SigmaDelta-frequency discriminator is verified using behavioral simulation