The problem of mapping neural nets onto massively parallel architectures is considered. The solution examined, based upon regular array structures, can support the mapping of any neural graph. In particular, the case of feed-forward multilayered nets is analyzed, and is proven that in this case the mapping suggested is easily implemented and optimizes a number of relevant figures of merit. The structure of nodes, I/O ports, and switches is taken into account with reference to the neural net case. It is seen that the claims of inherent fault tolerance for neural nets are not actually kept for all classes of faults of a digital implementation; moreover, it is considered that end-of-production defects require restructuring to grant nominal initial operation. An efficient and straightforward solution to the defect-tolerance problem is presented, allowing the most limited redundancy versus good harvesting characteristics.>

An approach to array fault tolerance is presented. A parametric tool for reconfigurability detection and reconfiguration of arrays is introduced. The underlying methodology is based on a partitioning algorithm to determine reconfigurability. After reconfiguration a compaction algorithm is used to optimize results. The application of this methodology to fault-stealing-based algorithms has shown good results in terms of the added required redundancy, even for fault distributions that were unreconfigurable when the reconfiguration algorithm was applied alone.>

The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system when faults occur: the type and distribution of faults can be defined by the designer. A diagnostic tool is integrated in APES to evaluate the fault-detection and error-correction capabilities of the system under observation. Another tool makes it possible to perform and evaluate the array reconfiguration after fault occurrence by adopting a user-defined strategy. Features including data entry (using a graphic editor or a hardware description language), the simulation engine, the fault injector, the diagnostic evaluator, and the restructuring/reconfiguration manager are discussed.>