Demo Data from VLDB 2026 / reviewers in the wild / expert
Susumu Adachi
dblp:82/3184
· DBLP profile ↗
7ranked-venue papers
0as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2Theory of computation · 2Systems, architecture and hardware · 1Databases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 87% Emerging computing paradigms · 13% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
asynchronous circuit design |
0.0 | 1 | 2004 | Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines · IEEE Trans. Computers 2004 |
Integrated circuit design › asynchronous circuit design
delay-insensitive circuit |
0.0 | 1 | 2004 | Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines · IEEE Trans. Computers 2004 |
Emerging computing paradigms
cellular automata |
0.0 | 1 | 2004 | Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines · IEEE Trans. Computers 2004 |
Methods — techniques the papers use, named apart from their topics
buffering line · 0.0bidirectional line · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Emergence of universal global behavior from reversible local transitions in asynchronous systems
Jia Lee, Susumu Adachi, Yunni Xia, Qingsheng Zhu |
Inf. Sci. | 2 |
| 2011 | A Partitioned Cellular Automaton Approach for Efficient Implementation of Asynchronous CircuitsabstractAsynchronous cellular automata (ACAs) have much promise as architectures for future computers with molecular-scale devices, since they are less likely to suffer from clock-related problems (i.e. wiring overhead, heat dissipation, etc.) and they are suitable for bottom-up manufacturing techniques due to their homogeneous structures. Computation on ACA can be accomplished by designing configurations on the cell space such that their evolutions emulate the operations of asynchronous circuits. However, these ACA models still require tens of transition rules, which may seem too high for efficient physical realizations. In this paper, we present a new cellular automaton in which each cell comprises a group of simple sub-cells that are locally coupled with each other. Based upon an effective set of asynchronous primitive operators, this novel ACA can be used to construct any arbitrary logic circuit, while the number of transition rules is less than half the number in previous ACA models. Jia Lee, Susumu Adachi, Ferdinand Peper |
Comput. J. | 2 |
| 2007 | Reliable Self-Replicating Machines in Asynchronous Cellular AutomataabstractWe propose a self-replicating machine that is embedded in a two-dimensional asynchronous cellular automaton with von Neumann neighborhood. The machine dynamically encodes its shape into description signals, and despite the randomness of cell updating, it is able to successfully construct copies of itself according to the description signals. Self-replication on asynchronously updated cellular automata may find application in nanocomputers, where reconfigurability is an essential property, since it allows avoidance of defective parts and simplifies programming of such computers. Jia Lee, Susumu Adachi, Ferdinand Peper |
Artif. Life | 2 |
| 2005 | Delay-insensitive computation in asynchronous cellular automata
Jia Lee, Susumu Adachi, Ferdinand Peper, Shinro Mashiko |
J. Comput. Syst. Sci. | 2 |
| 2004 | Universal Delay-Insensitive Circuits with Bidirectional and Buffering LinesabstractDelay-insensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DI-circuits and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra and Fussell presented an alternative universal set of primitive modules and claimed that there is no universal set of primitives satisfying Keller's conditions in which the largest number of input and output lines of each primitive module is less than five. We present new types of primitive modules, each having at most three input and output-lines and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input and output-lines of modules to be bidirectional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of Dl-circuits is especially useful for implementations on cellular automata - an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure. Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita |
IEEE Trans. Computers | 3 |
| 2003 | Embedding Universal Delay-Insensitive Circuits in Asynchronous Cellular Spaces
Jia Lee, Susumu Adachi, Ferdinand Peper, Kenichi Morita |
Fundam. Informaticae | 2 |
| 2000 | A Comparative Study of Gen-Duplicated GAs Based on PfGA and SSGA
Hidefumi Sawai, Susumu Adachi |
GECCO | 2 |