The four papers in this special section address new and emerging security trends for biomedial computations, devices, and infrastructures.

This paper is devoted to the design of fast parallel accelerators for the cryptographic \eta_T pairing on supersingular elliptic curves over finite fields of characteristics two and three. We propose here a novel hardware implementation of Miller's algorithm based on a parallel pipelined Karatsuba multiplier. After a short description of the strategies that we considered to design our multiplier, we point out the intrinsic parallelism of Miller's loop and outline the architecture of coprocessors for the \eta_T pairing over {\bf F}_{2^m} and {\bf F}_{3^m}. Thanks to a careful choice of algorithms for the tower field arithmetic associated with the \eta_T pairing, we manage to keep the pipelined multiplier at the heart of each coprocessor busy. A final exponentiation is still required to obtain a unique value, which is desirable in most cryptographic protocols. We supplement our pairing accelerators with a coprocessor responsible for this task. An improved exponentiation algorithm allows us to save hardware resources. According to our place-and-route results on Xilinx FPGAs, our designs improve both the computation time and the area–time trade-off compared to previously published coprocessors.

We propose compact architectures of the SHA-3 candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the Gifunction. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages, and to achieve high clock frequencies. With careful scheduling, we completely avoid pipeline bubbles. For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. We show for instance that a fully autonomous implementation of BLAKE-32 on a Xilinx Virtex-5 device requires 56 slices and two memory blocks.

Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. Software implementations being rather slow, the study of hardware architectures became an active research area. In this paper, we discuss several algorithms to compute the ηT pairing in characteristic three and suggest further improvements. These algorithms involve addition, multiplication, cubing, inversion, and sometimes cube root extraction over GF(3m). We propose a hardware accelerator based on a unified arithmetic operator able to perform the operations required by a given algorithm. We describe the implementation of a compact coprocessor for the field GF(397) given by GF(3)[x]/(x97+x12+2), which compares favorably with other solutions described in the open literature.

Since redundant number systems allow constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed, PKC involves large operands (160 to 1024 bits) and several researchers proposed carry-save or borrow-save algorithms. However, these number systems do not take advantage of the dedicated carry logic available in modern field programmable gate arrays (FPGAs). To overcome this problem, we suggest to perform modular multiplication in a high-radix carry-save number system, where a sum bit of the carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). Furthermore, we propose an algorithm which selects the best high-radix carry-save representation for a given modulus, and generates a synthesizable VHDL description of the operator.

In this paper, we propose a modified etaTpairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three.

The RN-codings, where "RN" stands for "round to nearest", are particular cases of signed digit representations, for which rounding to nearest is always identical to truncation. In radix 2, booth recoding is an RN-coding. In this paper, we suggest several multiplication algorithms able to handle RN-codings, and we analyze their properties.

The IDEA block cipher is a symmetric-key algorithm which encrypts 64 bit plaintext blocks to 64 bit ciphertext blocks, using a 128 bit secret key. The security of IDEA relies on combining operations from three groups: integer addition modulo 2/sup 16/, bitwise exclusive or of two 16 bit words, and modified integer multiplication modulo (2/sup 16/ + 1) which is the critical arithmetic operation of the block cipher. This is devoted to the study of efficient implementations of this operator on Virtex-II and Virtex-E devices. We investigate three algorithms based on a multiplication with a subsequent modulo correction which are particularly well suited for FPGA devices embedding small multiplier blocks. An IDEA processor based on such operators achieves a throughput of 8.5 Gb/s on a Xilinx XC2V1000-6 device. We also describe a new FPGA implementation of a modulo (2/sup n/ + 1) multiplier proposed by R. Zimmermann. The area of this operator is roughly twice smaller than that of previous FPGA implementations.

Field-programmable gate arrays (FPGAs) are large, fast integrated circuits-that can be modified, or configured, almost at any point by the end user. Within the domain of configurable computing, we distinguish between two modes of configurability: static-where the configurable processor's configuration string is loaded once at the outset, after which it does not change during execution of the task at hand, and dynamic-where the processor's configuration may change at any moment. This paper describes four applications in the domain of configurable computing, considering both static and dynamic systems, including: SPYDER (a reconfigurable processor development system), RENCO (a reconfigurable network computer), Firefly (an evolving machine), and the BioWatch (a self-repairing watch). While static configurability mainly aims at attaining the classical computing goal of improving performance, dynamic configurability might bring about an entirely new breed of hardware devices-ones that are able to adapt within dynamic environments.

RENCO is a reconfigurable network computer based on a Motorola 68360 processor for the conventional part, and four Altera Flex 10K130 or 10K250 FPGAs for the reconfigurable part. Therefore, the user has at his/her disposal up to one million programmable logic gates for executing his/her applications in a custom-made processor. RENCO runs a real-time operating system and a Java virtual machine.